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16.3

  • Diff Pair resize_respace issue

    Hi i am trying convert differential metrics (say increase my tracewidth) using 16.3 - resize respace DP command. It works fine with vertical and horizontal , but, 45 deg cline are not properly resized. primary gap is not maintained as intended and shows a D/S error. Pl suggest if you have overcome this...
    Posted to PCB Design (Forum) by Bala R on Tue, Sep 14 2010
  • Capture 16.3 Errors

    I'd like to report the following error in the 16.3 Version of Capture or Design Entry CIS: When converting a project from 16.01 to 16.3 Net Properties get mangled. I had a design all constrained with Propagation Delays and Relative Propagation Delays placed on a set of high-speed signal groups. When...
    Posted to PCB Design (Forum) by JWWS1 on Wed, Sep 8 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • why can't I remove the fixed property of a symbol?

    I want to move a symbol. but I can't move it, even I removed all the fixed property of that symbol. I tried it many time by different ways,picking all property option or each property option respectively. even though doing this, I still can't delete the symbol or move it ? why?
    Posted to PCB Design (Forum) by Churbill on Thu, Sep 2 2010
  • How can I import the property/value into allegro constraint from intell DDR_TLC/spreadsheet

    For pin delay resson, I need to import the package length from a spreadsheet. How can I import the property/value into allegro constraint manager from intell DDR_TLC/spreadsheet. By doing this, the length matching could be matched well. I must indicate that , there is no 'PIN name ' coloumn in...
    Posted to PCB Design (Forum) by Churbill on Wed, Sep 1 2010
  • How to open *.BD1 files ?

    I have some *.BD1 files , but I cann't open them by using orCAD 16.3 . How can I open these files ? Could someone help me ? Tanks a lot !!!!
    Posted to PCB Design (Forum) by Hanson on Tue, Aug 24 2010
  • problem of plotting a Schematic in Design Entry HDL?

    when I select " Fit To Page" and use Adobe pdf printer to plot my design, the complete schematic page can not be fully displayed in one page, some of the schematic(right-bottom part) is missing, as the figure below. What's the problem? Should I change some other setting? By the way, I use...
    Posted to PCB Design (Forum) by starlin on Sat, Aug 21 2010
  • Problem with thermal relief size

    Hi, I'm a newbie. I have some problems with Orcad PCB Designed and thermal relief. I have edited a pad and defined this pad for all the layers: regular pad: circle 60 thermal relief: circle 80 antipad: circle 80 When I create a dynamic shape to create a copper pour region the ray of thermal relief...
    Posted to PCB Design (Forum) by CarloL on Tue, Aug 17 2010
  • Pad Seed Points

    Using OrCAD PCB Designer v16.3.S009 I would like to know how to control the copper seed point on a particular symbol, but not the whole design. I have a shield over a part that has 4 pads that are all GND. This part is on the top layer which has a GND copper pour dynamic shape. When I smooth the shapes...
    Posted to PCB Design (Forum) by melview1 on Wed, Aug 4 2010
  • Differential Pairs

    Using OrCAD PCB Designer v16.3.S009 Can anyone help me on how to route a differential pair to be the same length and same separation during the whole route? I'm sure there's some properties or modes I am missing that makes this easier than doing it manually. Thanks. --Mark
    Posted to PCB Design (Forum) by melview1 on Thu, Jul 22 2010
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