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  • how to import the netlist into allegro created by orcad capture??

    Hi mates,.. I have generated the netlist for allegro (5 schematic pages ) using orcad capture. that is, having three dat files.. As a next step, i am trying to import the netlist into allegro PCB editor. But, i couldnt.it just showig the blank page. Can u please clarify that what may be the problem and...
    Posted to PCB Design (Forum) by Prince Moses on Tue, Feb 8 2011
  • How can I view a (.brd) file created on cadance 16.3 on a 16.2

    I have a file created on cadence software 16.3 but only hace access to 16.2. Is it possible to view such a file on 16.2 version of the software?
    Posted to PCB Design (Forum) by Ger Rover on Thu, Jan 27 2011
  • back annotation via command line

    Is there any options that I can use command line interface to run back annotate to update the schematic using a .swp file? or is it possible to launch a particular schematic and then use an initialization file in that directory that commands the back-annotation.
    Posted to PCB Design (Forum) by powerit46 on Tue, Jan 25 2011
  • Add text using text script in concept HDL

    Hello Is there a file in the sch_1 directory that I can edit to add (or update) a text string that will be shown when I open the design page? Thanks
    Posted to Feedback, Suggestions, and Questions (Forum) by Nimrodt on Thu, Dec 23 2010
  • Error: Could not find symbol:

    I'm attempting to create my first PCB using PCB Editor. I'm stuck on this error message. ERROR: Could not find symbol: C161 / CAP_0402_0R1UF_X7R_10V_C0402_0. / C0402 I have a feeling it's because all of my footprint libraries are inside my project folder and not in the default director. I...
    Posted to PCB Design (Forum) by Squintz on Fri, Dec 10 2010
  • Orcad 16.2 - Create netlist error "CAP[0020]"

    Hi, I recently upgraded both computer,os and orcad. I am currently running Win 7- Orcad 16.2. Everything seems fine except for the creating a net list. The window flags me with " [CAP0020] Unable to open netlist format file:netlist.dll" I do see this .dll with the rest of the .dll files. Please...
    Posted to PCB Design (Forum) by Strickland on Sat, Sep 11 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010

    For Part Table Files with large amount of package types (i.e. res & caps), when a value is changed or a part is added, regardless if the part is in a project, HDL is notifying and forcing the user to update their schematic when these parts are not even used in their given design. This adds a lot...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010

    We currently distribute our global library over a network folder using hard coded Enviromental Veriables. The problem is that we have no way of knowing when the library was last updated. This can cause users to be un-aware of recent library updates or if they are using old revisions of the library (due...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
  • How much is a license of allegro16.2

    what a piy! though I work as a PCB Engineer for many years. till now, I don't know the price of Allegro exactly. Is there anybody know how much a license of allegro 16.2 is?
    Posted to PCB Design (Forum) by Churbill on Wed, Aug 18 2010
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