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16.2,PCB design

  • Orcad 16.2 Create Netlist

    Hi, I recently installed Orcad 16.2 on windows xp, and when in orcad capture there are no menus under tools. Has anyone seen this before, or know how to fix it? Thanks in advance. Martyn
    Posted to PCB Design (Forum) by Martyn91 on Fri, Oct 21 2011
  • TestPrep in OrCAD PCB Editor

    Ahoy there, I'm using OrCAD PCB Editor to create ICT testpoint. I'm trying to create a report to print net name with its associate testpoint so I can see which nets have testpont and which hasn't. How can I mark nets that already have testpoint in the DSN, so when I run testprep with "Add...
    Posted to PCB Design (Forum) by Alfandari on Wed, Apr 13 2011
  • Cannot place parts in PCB editor 16.2

    I am a newbie and am trying to design my first PCB. I've made my schematic, pads, footprints, generating netlist and even created my board outline. But I cannot place any of my parts! I cannot find/see my "Placement Edit" button (only Generaledit and Etchedit). And when I try to Place ...
    Posted to PCB Design (Forum) by karac on Wed, Feb 23 2011
  • How to create drill location report

    Hi all, Can anybody help me, How to create drill location report from a .brd file (Tool: Allegro PCB design 16.3)? Below is an example from an orcad layout plus file. COMMENTS DRILL TOOL XCOORD YCOORD ------------------------------------------------------- Holes (Padstacks with no pads defined) 2.60...
    Posted to PCB Design (Forum) by rinj on Thu, Feb 17 2011
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • LIBRARY REVISION VISIBILITY

    We currently distribute our global library over a network folder using hard coded Enviromental Veriables. The problem is that we have no way of knowing when the library was last updated. This can cause users to be un-aware of recent library updates or if they are using old revisions of the library (due...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
  • round ends on lines

    Hello Folks, How do you get a line to have rounded ends instead of square ends. This is for a part footprint using Allegro 16.2. Thanks, Tom
    Posted to PCB Design (Forum) by Thomas M on Thu, May 27 2010
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