Home > Community > Tags > 16.2/Capture CIS
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

16.2,Capture CIS

  • omit / ignore parts in a BOM(BOM_IGNORE?), also label as "do not stuff" automatically in BOM

    I've looked at several forms/user guides/help documents and I'm unable to find the answers I'm looking for. I'm using orcad capture 16.2. I do *not* have CIS :'( 1. Is there a straightforward way to keep schematic compenonts off of the BOM. e.g. a PCB pad, fiducials, etc. EDIT: I'm...
    Posted to PCB Design (Forum) by cobcra on Tue, Dec 3 2013
  • Orcad quits unexpectedly

    Hi - after years of no trouble running OrCAD it suddenly won't start on my XP machine. In the 16.2 version it pops up "The application has quit unexpectedly". I've tried all the tricks I know (reinstall, reload graphics drivers, snip the .ini files) -- can't figure this one out...
    Posted to PCB Design (Forum) by redwire on Sun, Nov 27 2011
  • [HELP] Allegro PCB file lost

    Hi guys, I just met a big problem with Allegro 16.2. I have layout all the pins on my 4-layer pcb. But I found one component had a wrong pin net name, so I updated it in Capture. After then, I re-open the .brd file and want to update the pcb, at this time, Allegro PCB design GXL pop up a warning! "WARNING...
    Posted to PCB Design (Forum) by cshinyc on Sun, Sep 11 2011
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Component placement error in Allegro 16.2

    Hello folks, Allegro keeps giving me an error message everytime i try to Place Manually a symbol (6032 CAP)...the message says: ""E- (SPMHGE-82): Pin numbers do not match between symbol and component. Run dev_check on device file for more information."" I have saved the *.dra file...
    Posted to PCB Design (Forum) by Fadi on Fri, Apr 9 2010
Page 1 of 1 (5 items)