Home > Community > Tags > 16.2/16.3/Logic synchronization failed/EDIF netlist from ConceptHDL schematic/padstack change/DRC error/netlist files/Allegro PCB SI/Auto Silkscreen Line Width/PCB Layout and routing
 
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16.2,16.3,Logic synchronization failed,EDIF netlist from ConceptHDL schematic,padstack change,DRC error,netlist files,Allegro PCB SI,Auto Silkscreen Line Width,PCB Layout and routing

  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
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