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14nm

ARM TechCon: Inside Story of a 14nm FinFET Tapeout

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
FinFETs, Tri-Gate Transistors Promise Low Power – But Pose Some Design Challenges

At 14nm and below, it's a good bet that many IC designs will use a new 3D transistor technology called "FinFET" (or, to use Intel's term, "Tri-Gate"). With the promise of greatly reduced power at a given level of performance, there's much to like about FinFETs. But there...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 23 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges

Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49 th DAC in San Francisco. Tuesday June 5 Addressing...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 14 2012
See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

It's that time of the year again! The 49 th Design Automation Conference ( DAC 2012 ) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 25 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 1 2012
ISQED Keynote: 20nm From a Custom/Analog Perspective

Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design ( ISQED 2012 ) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 21 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm

The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 19 2012
TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 14 2012
2012 CES: Top 3 Trends Impacting EDA This Year

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't personally attend CES this year, I had two trusted...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Jan 17 2012

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14nm

ARM TechCon: Inside Story of a 14nm FinFET Tapeout

FinFETs, Tri-Gate Transistors Promise Low Power – But Pose Some Design Challenges

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges

See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

ISQED Keynote: 20nm From a Custom/Analog Perspective

On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

2012 CES: Top 3 Trends Impacting EDA This Year