Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> 14nm/20nm/Industry Insights
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
14nm,20nm,Industry Insights
10nm
12" wafers
14XM
16nm
2(x)nm
2.5D IC
2012
20nm tools
28nm
3D
3D extraction
3D IC
3D transistors
3D-IC
7 nm
advanced node
Analog
ARM
ARM Techcon
blogs
Cadence
Cadence at DAC
Cassidy
CDN Live
CDN Live!
CDNlive
CDNLive!
CDNLive! Silcon Valley
Chenming Hu
Chian
Choi
co-development
collaboration
colorization
common platform
common platform forum
Cortex-A15
Cortex-A7
Cortex-A9
Cortex-M0
cowbell
CoWoS
custom
Custom IC
custom/analog
DAC
DAC 2012
DAC breakfast
DAC breakfasts
Denali Party
Design Automation Conference
design rules
DFM
Double Patterning
double patterning aware
DRC
e-beam lithography
electromigration
EM
embedded software
emulation
Encounter
ESL
EUV
FinFET
FinFets
GlobalFoundries
HKMG
IBM
IBM: Samsung
LELE
Liebmann
lithography
Patel
Patton
placement
routing
SADP
Samsung
sidewall image transfer
SystemVerilog
Tom Beckley
Top Ten
transistors
Tri-Gate
triple patterning
TSMC
TSV
tutorials
two-color mapping
Ubuntu
UVM
variation
Verification IP
videos
VIP
Virtual Technology Forum
Virtuoso
Yeric
yield
Common Platform Forum Keynotes: 14nm FinFETs and Beyond
How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 6 2013
Top Ten Cadence Community Blog Posts of 2012
In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 1 2013
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Nov 2 2012
FinFETs, Tri-Gate Transistors Promise Low Power – But Pose Some Design Challenges
At 14nm and below, it's a good bet that many IC designs will use a new 3D transistor technology called "FinFET" (or, to use Intel's term, "Tri-Gate"). With the promise of greatly reduced power at a given level of performance, there's much to like about FinFETs. But there...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 23 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm
What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 12 2012
Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges
Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49 th DAC in San Francisco. Tuesday June 5 Addressing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party
It's that time of the year again! The 49 th Design Automation Conference ( DAC 2012 ) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 25 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning
Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 1 2012
ISQED Keynote: 20nm From a Custom/Analog Perspective
Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design ( ISQED 2012 ) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 21 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm
The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 19 2012
Page 1 of 2 (11 items) 1
2
Next >