Home > Community > Tags > .lib
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

.lib

  • Programmable Logic Wizard Problem

    Hi everyone, I'm having a trouble creating a new project using the programmable logic wizard in OrCAD Capture. The vendor and family list is empty so I can't create a new project. How to fix this issue? Please help me as I'm fairly new to this software. Thanks.
    Posted to Digital Implementation (Forum) by ammaro90 on Sun, Apr 27 2014
  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • Set default load in Library generation

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler uses a a load I am unaware of . Is is possible for me to generate library file which defines a default load to all pins unless stated ? . 2...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Default Load in RTL Compiler

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler does produce a result but I am uncertain of which load it is assuming d what toggle rate or stimuli is being considered... . 2) I want to set...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Library for Verilog

    Hi, I have a question about creating symbol from verilog.v on vi editor. After finishing the codes and type :wq the following error occurs ncvlog: *W, DLCPH (/export_w19/umc130/cds.lib,4): cds. lib Invalid path ' /export_w19...../analogLib' (cds.lib command ignored). DEFINE cdsDefTechLib $CD_INST_DIR...
    Posted to Custom IC Design (Forum) by Cahe248 on Thu, Nov 15 2012
  • Bringing Static Analysis Methods to Mixed Signal Designs

    Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs. The functional verification of mixed -signal designs has never been completely possible. It is very common to use behavioral models of analog/mixed-signal blocks during the full chip...
    Posted to Mixed-Signal Design (Weblog) by RajendraPratap on Fri, Aug 26 2011
  • Internal error with topology.c

    Hi, When I try to run a Spectre dc and trans simulation with my 8-bit-adder circuit, have an internal error stopping the simulation. I get the following messages in the spectre log window: 1) the usual "unable to compile ahdlcmi module library" message (which has not stopped my simulations...
    Posted to Custom IC Design (Forum) by CPete on Thu, Jun 2 2011
  • Generating .lib file from layout

    Hi, I am trying to generate my own .lib file from the layout I've designed in Virtuoso. I tried to use SignalStorm, but figured out that I do not have license for it. Could anyone please suggest any other tool to do this? Also, does SignalStorm come along with the standard university package? I remember...
    Posted to Custom IC Design (Forum) by govilv on Mon, Jun 22 2009
Page 1 of 1 (8 items)