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Page 1 of 2 (16 items) 1 | 2 | Next >

Re: Exclude macros from addMetalFill
I also find nothing options to exclude Macro for adding metal fill. i often create routing blockages over Macros.

Posted to Digital Implementation (Forum) by icmaple on Tue, Aug 30 2011
Re: Redirecting into a file
getReport {get_pins -of_objects <CELL_NAME> } > xx.rpt

Posted to Digital Implementation (Forum) by icmaple on Thu, Sep 9 2010
about postMask ECO
there is a NAND gate added in non-clock path. For postMask eco flow: ################################### ## !! post_mask eco flow ################################### loadConfig ./${cell_name}.conf 0 set rda_Input(ui_netlist) $econetlist commitConfig #loadFPlan ${cell_name}.fp ecoDefIn -postMask -suffix _spare -reportFile ecoDefIn.rpt ...

Posted to Digital Implementation (Forum) by icmaple on Tue, Jan 19 2010
about " feResource cpu "
can somebody detail the usage of this command? thanks

Posted to Digital Implementation (Forum) by icmaple on Tue, Nov 17 2009
Re: an Error during placement?
thank you very much,BobD. I learnt much from your example. as for my issue, i found the reason which was a wrong definition of generated clock. it should be -edge { 1 5 11}. so it is inconsistent with logic topology.

Posted to Digital Implementation (Forum) by icmaple on Sat, Nov 7 2009
Re: how to prevent inserting clkbufs along clkpath in the specified moudle??
thanks. in version 8.1.2 there is a cmd " DontTouchNet" can be used in ctstch file.

Posted to Digital Implementation (Forum) by icmaple on Mon, Nov 2 2009
Re: an Error during placement?
hello BobD, sorry too late reply. create_clock -name "clk3" -add -period 6.66 -waveform {0.0 3.33} [get_ports clk_adc_in] Why it only reports Falling Edge latency path can not be found?

Posted to Digital Implementation (Forum) by icmaple on Mon, Nov 2 2009
Timing Engine isues **ERROR: (TA-152) complaining about generated clock edges (was: an Error during placement?)
During placement, it issue below Error hint , and placement continues..... **ERROR: (TA-152): A latency path from the 'Fall' edge of the master clock at source pin 'clk_adc_in' to the 'Fall' edge of generated clock 'clk18' at pin 'u_center_ctrl/u_clk_gen/u_clkmx2x8m_46/Y' cannot be found. ...

Posted to Digital Implementation (Forum) by icmaple on Wed, Oct 28 2009
about bufferTreeSynthesis ??
if Net resetn connects RN port of many different SDFF ( X2 X4 ..) , when i use bufferTreeSynthesis cmd, Need I use its option: -leafPorts for thest different SDFF.? bufferTreeSynthesis consider what type of Pin/Port as Leafport by default??

Posted to Digital Implementation (Forum) by icmaple on Tue, Oct 27 2009
about mechanism of CTS ??
After cts tracing the clock path, cts will divide many steps to do local cts (then use macro model to do cts upper level) from Sinks up to source clock as below for example: **** CK_START: Update Database (mem=3265.2M) 36 Clock Buffers/Inverters inserted. **** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, ...

Posted to Digital Implementation (Forum) by icmaple on Thu, Oct 22 2009

Page 1 of 2 (16 items) 1 | 2 | Next >

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