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 Community Search 

Page 1 of 2 (13 items) 1 | 2 | Next >
  • Re: dummy net assignments of pins and shapes in an inherited footprint
    LOL! Yeah - I suppose it could be worse :D While this discussion was going (and between meetings); I left the DRC flags in place and updated my design to use the new "improved" symbol, and as expected; they all went away as soon as everything got attached to signal gnd ;) Was this maybe a feature that existed in a previous version of ...
    Posted to PCB Design (Forum) by mpfleger on Fri, Apr 25 2014
  • Re: dummy net assignments of pins and shapes in an inherited footprint
    Yeah; this is pretty much what I gathered. It's just a bit maddening to see one pin, that magically has retained its "dummy net" status, be the only one of the group that doesn't have a DRC flag =/ It would be nice to know how that was done in the first place. Cheers, M 
    Posted to PCB Design (Forum) by mpfleger on Fri, Apr 25 2014
  • dummy net assignments of pins and shapes in an inherited footprint
    Hi all. So here's a fun one. I have an SMA connector footprint (I've inherited), that includes a shape on the top layer, obstensibly for impedance control reasons. Now here is where things get interesting. I've had to change some of the padstacks to accomodate the more relaxed (read: sane) specs of a fab house. Suddenly the changed ...
    Posted to PCB Design (Forum) by mpfleger on Fri, Apr 25 2014
  • Re: How to add a company logo or a marking seregraphy with "Allegro PCB Design"
    Hi Dave, I've been playing with logomaker, and I have a question... As I understand it; the intermediate file format used in the conversion is SVG (due to potrace digesting a bitmap), and this is fed to the latter part of your skill program for conversion into lines. In this case; is there an easy way to pipe SVG logos directly through the ...
    Posted to PCB Design (Forum) by mpfleger on Mon, Nov 18 2013
  • Re: startup config options for Allegro
    oldmouldy and fxffxf: Nicely done gents! Your suggestions were able to help me nail down what was going on, and finally to deal with the problem. Now when the rest of the office workstations get moved to Win7 and Cadence 16.6 - we have a way of circumventing the GPO fun :D Thanks a bunch! -M 
    Posted to PCB Design (Forum) by mpfleger on Thu, Aug 8 2013
  • Re: startup config options for Allegro
    Hi fxffxf, Now that was simultaneously interesting and somewhat infuriating: This location contains an allegro.ini file, which (surprise surprise) does specify the wrong version of Allegro WRT our license file. Apparently *somebody* set up GPOs to assign our HOME vars to point to a directory on a server. This would explain why pcbenv installed ...
    Posted to PCB Design (Forum) by mpfleger on Thu, Aug 8 2013
  • Re: startup config options for Allegro
    Hmmm... I found these two lines in my allegro.ini file (in the pcbenv folder): base_license=Allegro_performance option_licenses=Allegro_PCB_HighSpeed_Option   It's like this file is not being read at all, and the files show no changes (by timestamp) since the day I built up this workstation and installed Cadence (June 13). I renamed ...
    Posted to PCB Design (Forum) by mpfleger on Wed, Aug 7 2013
  • startup config options for Allegro
    Hi all. I'm running 16.6 on Win7, and am having some interesting problems. In my attempts to diagnose exactly what's going on, I stumbled across a posting where someone outlined the command line options for starting allegro. The file:  C:\Cadence\SPB_16.6\share\pcb\batchhelp\allegro.txt - suggests launching with the executable with ...
    Posted to PCB Design (Forum) by mpfleger on Wed, Aug 7 2013
  • Re: top side via tenting on thermal pad
    Hi Robert. I've been playing around with these footprints, and checking the actual gerber output to see if it agrees with what I'm seeing in Allegro. I'm still using 16.5, btw. The primary issue I'm trying to raise lies with the provision that exists (in Padstack Designer) to put multiple drills into a padstack, even if ...
    Posted to PCB Design (Forum) by mpfleger on Mon, Dec 10 2012
  • Re: top side via tenting on thermal pad
    Hi. I've been working with a similar design problem. You can see that Q3 and Q4 have "multiple drill" via arrays inside their drain pads, and there's a little green halo around each one which demarcates the "void" inside the soldermask shape. This padstack has no soldermask layer attached to it; that layer is defined ...
    Posted to PCB Design (Forum) by mpfleger on Mon, Dec 3 2012
Page 1 of 2 (13 items) 1 | 2 | Next >