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 Community Search 

Page 1 of 1 (5 items)
  • Re: Toggle coverage on SystemVerilog interfaces
    Hi Max, Toggle coverage is not yet supported for SV interfaces. If you email me your contact inf, I can be sure to notify you when support is added.  My email is nlin@cadence.com.  In the future, if you have questions about the functionality of the tools, be sure to go to support.cadence.com Best Regards, Nancy
    Posted to Functional Verification (Forum) by nlin on Thu, Oct 29 2009
  • Re: Facing difficulty in fucntional coverage using NCSim
    Hi kolipaka, User-defined cross bins will be supported in the next release of the software (INCISIV9.2)  which is scheduled to be released by next week.   If you have any follow up questions, be sure to log onto http://support.cadence.com and file a Service Request with the Customer Support team.  Regards, Nancy
    Posted to Functional Verification (Forum) by nlin on Wed, Oct 7 2009
  • Re: ICCR, how to disable fullcase default branch scoring
     Hi RyanLV, Your post had been posted in the wrong forum, but was put in the Functional Verification forum just today.  In the future, if you have any questions with regards to the IUS tools you can open a Service Request at http://support.cadence.com.  One of our knowledgeable AEs should be able to help you.   With regards ...
    Posted to Functional Verification (Forum) by nlin on Thu, Sep 24 2009
  • Re: ICCR union usage
    Hi, The union command requires that the design is identical.  I think what you would like to accomplish can be done with the merge command.  The merge command will merge what is identical in primary and secondary databases, and ignore items in the secondary database that's not in the primary database.  There is also a union ...
    Posted to Functional Verification (Forum) by nlin on Mon, Sep 14 2009
  • Re: merging code coverage from different design databases
     Hi,  In order to merge the coverage databases, you'll need to set the DUT to merge and use the merge iccr command.    i.e. set_dut_modules subSystemA subSystemB This is if subSystemA and subSystemB are the actual module names of the blocks instantiated inside the chip  which you want to merge Then use the merge ...
    Posted to Functional Verification (Forum) by nlin on Tue, Aug 4 2009
Page 1 of 1 (5 items)