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 Community Search 

Page 1 of 1 (9 items)
  • *ERROR: (ENCOAX-41): Cannot create an instance in a hierarchy where the occurrences are not unique
     Hello,  I have a P&R-ed design (let's call it MultiA) in Encounter with no violations. I'm trying to export it in Virtuoso using OA database. While doing this, I receive the following errors: **ERROR: (ENCOAX-41):   Cannot create an instance in a hierarchy where the occurrences are not unique **ERROR: ...
    Posted to Digital Implementation (Forum) by konx on Mon, Jul 30 2012
  • Re: ncelab: segmentation of a signal
     [quote user="diablo"] Are you using TIEHO and TIELO cells while synthesizing the verilog design?  [/quote]   Hi diablo, we are not using TIEHO and TIELO cells because they are not present in the library we are using. It seems indeed to be problem, but until now the only way to avoid it was to synthesize the design ...
    Posted to Digital Implementation (Forum) by konx on Mon, Jul 18 2011
  • From Verilog to layout - Flow problems
     Hi, sorry for this long post but I'm having some issues with a flow that ideally would start from a Verilog description and end with a layout. I try to describe shortly what I do and where I find problems. 1) Describe the design in Verilog: create 2 different cells (controller and counter). So, for each cell I have a Verilog ...
    Posted to Digital Implementation (Forum) by konx on Sat, Jul 16 2011
  • ncelab: segmentation of a signal
     Hello everyone. I try to be specific: - I wrote some Verilog modules for a design (counter, shift registers, etc..) - Using RTL Compiler I do the synthesis of the design - I load the desing in Encounter and I do P&R - Send back the layout to Virtuoso using OpenAccess database - Encounter produces a post-P&R verilog netlist: ...
    Posted to Digital Implementation (Forum) by konx on Fri, Jul 15 2011
  • Sroute and vias in Encounter
    Hi. I have the following problem: I'm using Encounter. I have a 'L-shape' floorplan, and I can put power rings (so, VDD and VSS lines) only in vertical direction using M2 layer (and this is working). Then, I have to connect these lines on opposite sides with horizontal connections (using M1). At the moment to do it I'm using the ...
    Posted to Custom IC Design (Forum) by konx on Fri, Aug 21 2009
  • Encounter OpenAcces: problems with exporting design
    Hi! I have the following problem: I'm running an Encounter session in a directory called "Encounter". In this directory I put: a) pixel.conf file b) floorplan.fp files c) pixel_synt.v (verilog netlist) d) pixel.sdf file e) lib.defs file: in this file I have the paths pointing to many libraries, in particular a library called ...
    Posted to Custom IC Design (Forum) by konx on Tue, Aug 18 2009
  • Re: Layout: from Encounter to Virtuoso
    Thank you very much for your help, more or less the problem is solved now :)  Francesco.
    Posted to Custom IC Design (Forum) by konx on Thu, Aug 6 2009
  • Re: Layout: from Encounter to Virtuoso
     Hi Marie,  thank you for your aswer.  As you said, I found the OpenAccess database as a quite good method to export layout from Encounter to Virtuoso. I still have a couple of question about this new method: 1) When I use the "Import Design" GUI in Encounter and select Advance tab there is a OpenAccess form. In the ...
    Posted to Custom IC Design (Forum) by konx on Wed, Aug 5 2009
  • Layout: from Encounter to Virtuoso
    Hi!  I'm a new user of the forums :) This is the problem I have at the moment:  I have a complete design in Encounter of a block called Pixel, and I want to export it to cadence virtuoso. Reading on internet and the help, I've seen that I have to export a GDSII file (basically, I can produce 2 file: the outputStream ...
    Posted to Custom IC Design (Forum) by konx on Mon, Aug 3 2009
Page 1 of 1 (9 items)