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 Community Search 

Page 1 of 2 (11 items) 1 | 2 | Next >
  • Re: SDF Errors
    Hi Scrivner, I have a situation similar to that of this thread. Some of our cells have sdf annotations unspecified in the verilog (giving a elaboration warning), but I also have missing sdf annotations requested in the verilog (thus leaving the default check values of 1 ns). I looked a bit but I'm still stuck. Basically, if I use my hdl ...
    Posted to Digital Implementation (Forum) by MzQuarter on Thu, Aug 4 2011
  • ELC - illegal "complementary" in gate file
     Hi all,  I am trying to characterize a differential receiver using elc by using a gate model to specify the cell's behaviour. For the gate file, I copied the example given in the user guide, since its behaviour is the same as our custom cell: DESIGN (DIN);     //PORT SECTION;     INPUT P ...
    Posted to Digital Implementation (Forum) by MzQuarter on Sat, Jul 2 2011
  • Re: Encounter 8.1 vs 9.1 sdf generation
    Hi Diablo and Martinage, I had some time to come back to this problem, and found what I was looking for thanks to your help and pointers. Here is what I did: The project comes with wcbc already setup, so I added a typical view in MMMC by following the user guide chapter on MMMC (this thread: ...
    Posted to Digital Implementation (Forum) by MzQuarter on Fri, Oct 29 2010
  • Re: Encounter 8.1 vs 9.1 sdf generation
    Thanks a lot for the info, it helps me take a new look on the issue. Cheers.
    Posted to Digital Implementation (Forum) by MzQuarter on Tue, Oct 19 2010
  • Re: Encounter 8.1 vs 9.1 sdf generation
    Hi diablo, Thanks for the info. Let me clear up my intent, it might help. Before starting on the real design layout, I'm doing a first run around the whole back-end process using a very small project to iron out any problems I might run into. It real project is mixed signal, with many small analog instances at the bottom of the hierarchy ...
    Posted to Digital Implementation (Forum) by MzQuarter on Mon, Oct 18 2010
  • Re: Encounter 8.1 vs 9.1 sdf generation
    Hi diablo, Here is what I do through the GUI, with a little more detail, (same for both versions). 1- Start encounter 2- Restore design from an encounter format 3- Do RC extract (simplest kind, not sign-off) 4- Calculate timing It translates to the following commands in the log file, after loading the project: Encounter 8.1:  ...
    Posted to Digital Implementation (Forum) by MzQuarter on Mon, Oct 18 2010
  • Encounter 8.1 vs 9.1 sdf generation
    Hi, I've used Encounter 8.1 for past projects to generate sdf back-annotation for simulation and it worked great. Now we've moved to Encounter 9.1, but the exact same 8.1 encounter project reloaded in 9.1 gives different results. First of all, the middle field ("typical", my guess) is no longer present, and when I load the sdf ...
    Posted to Digital Implementation (Forum) by MzQuarter on Mon, Oct 18 2010
  • Re: mixed signal design flow
    Hi all,  I'm also working along the same lines, and have two questions regarding simulation with this kind of mixed-signal flow. Lucky for me, I have access to the gds files, so I can run DRC and LVS on my full design in virtuoso. So no problem there. However, I'm hoping to use sdf back-annotation for digital cells and full spectre ...
    Posted to Custom IC Design (Forum) by MzQuarter on Fri, Oct 15 2010
  • Encounter 9.1 - Synthesize Power Plan menu
    Hi, I am currently working through an old encounter workshop, with a DTMF design, located at share/fe/gift/tutorials/dtmf in my encounter 9.1 install directory.  I got the artisan files from the training course page. The workshop document is dated january 2007, and written for SoC encounter 6.20. In section 6, page 29, the tutorial makes an ...
    Posted to Digital Implementation (Forum) by MzQuarter on Mon, Jul 12 2010
  • Re: Mixed signal post-layout simulation flow – spectreVerilog – delay extraction problem
    I've managed to find the problem. To have proper capacitance values in the spf file, some settings in CDF for the auLvs view of pcapacitor must changed. To make it work, I changed the following settings in the simulation settings : instParameters : C componentName : pcapacitor propMapping : nil C c After changing this, I also noted that ...
    Posted to Digital Implementation (Forum) by MzQuarter on Mon, Jul 27 2009
Page 1 of 2 (11 items) 1 | 2 | Next >