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 Community Search 

Page 1 of 1 (6 items)
  • Re: How to find ThroughPin(s) for generated clock
     Hi Kari, thank you for your suggestion. It seems we were simply misled by assuming that the ThroughPin entries are mandatory for every clock divider - as a result, we were trying to locate the source of our problem at the wrong place. I think we have found some potential issues by now.   Thank you all for your clarifications and ...
    Posted to Digital Implementation (Forum) by MMode on Thu, Jul 1 2010
  • Re: How to find ThroughPin(s) for generated clock
    Thank you for your hints, that was very helpful - we considered the ThroughPin spec to be mandatory for every generated clock, this does not seem to be correct. We checked the clock trace, it shows that the registers in questions are sinks of the clock tree, so you are right, the ThroughPin does not seem to be necessary here. However, we do not ...
    Posted to Digital Implementation (Forum) by MMode on Wed, Jun 30 2010
  • Re: How to find ThroughPin(s) for generated clock
     Hi Rajesh,   thank you for your suggestion. We tried that but the ThroughPin section was empty in the resulting file. However, with this we were unable to reach timing closure.
    Posted to Digital Implementation (Forum) by MMode on Wed, Jun 30 2010
  • How to find ThroughPin(s) for generated clock
    Hi all, in our design we use a number of generated clocks, i.e. the main clock is for instance divided by 13339. The clock dividers are specified as generated_clock in the SDC file. Now, we would like to build a clock tree for the main clock including the generated clock domains. This should be possible with the ThroughPin feature of the ...
    Posted to Digital Implementation (Forum) by MMode on Wed, Jun 30 2010
  • Re: missing vias in stacked power rings
     Hi Bob, thanks a lot for your response. We are working in a process with shrink factor, i.e. the 1000 microns wire will actually be 70 microns wide in final dimensions. The shrink factor was specified using ui_shr_scale in the configuration file. We have thoroughly checked the LEF files as well as the design rule specification documents, ...
    Posted to Digital Implementation (Forum) by MMode on Tue, Jan 26 2010
  • missing vias in stacked power rings
     Hi all,   we are working in a 5 metal layer process with Encounter 5.2. In our design, we have decided to stack the power rings, i.e. the VSS ring is on metal layer 1 and the VDD ring is in the same position but on metal layer 5. However, we are confronted with the following problem during power routing: If the ring's width is ...
    Posted to Digital Implementation (Forum) by MMode on Thu, Nov 19 2009
Page 1 of 1 (6 items)