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Page 1 of 1 (4 items)
  • Re: Best flow to map most key points before compare
     Thanks for your reply.   It's exactly I want. My design is NonEq and the runtime is very big but I wanted to discover if I can help LEC to map more faster the key points just to reduce the runtime.  Regards 
    Posted to Logic Design (Forum) by AntonioL on Thu, Mar 29 2012
  • Re: How to report leaf cell area
     I used a"done-by-me" tcl script to do this.  For memories and hardmacros in general you could use report gates instead of report area.
    Posted to Logic Design (Forum) by AntonioL on Wed, Mar 28 2012
  • Do you have issues using multibit flops
     Hi All, I used multibit flops (dual and quad) for my last synthesis run and when I have 1st_mapped_Gate2Gate_with_multibit_flops Conformal runs I have a lot of not-equivalent points due to them. I asked to Cadence support for this and they answered me that my netlist had missing "CDN_MBIT_" prefix for multibit flops. I ...
    Posted to Logic Design (Forum) by AntonioL on Wed, Mar 28 2012
  • Best flow to map most key points before compare
     Hi All, I saw that Conformal has "most than 1/3 of key-points mis-matched by names". So I want to help it to map more key-points. I used default value for set_mapping_method for my 1st Gate2Gate run. Could I use different set_mapping_method commands incrementally to map most key-points?   Which is the best flow to do ...
    Posted to Logic Design (Forum) by AntonioL on Wed, Mar 28 2012
Page 1 of 1 (4 items)