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 Community Search 

Page 1 of 4 (34 items) 1 | 2 | 3 | 4 | Next >
  • Logic Design Forum Posting Guidelines
    Thanks for being part of the Cadence Community. Below are a few guidelines on using the forums. Use descriptive subjects. "Problems with LEC mapping" is good. "Need help” isn’t.Please start new threads for new topics. Don’t reply to existing threads with unrelated discussion. This helps users scan posted ...
    Posted to Logic Design (Forum) by tstark on Thu, Feb 6 2014
  • Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist
     You should be able to use this option with write_hier_compare_dofile in TCL. It will have to be valid TC, escaped etc.  Maybe try with something simple first and verify it works. There are some small sample testcases in the installation tree: share/cfm/lec/demo If it is too much of a problem try going into VPX mode (not TCL ...
    Posted to Logic Design (Forum) by tstark on Wed, Feb 5 2014
  • Re: conformal_lec 12.0
      Are you working with power ports? If not, it seems like the library files need to be cleaned-up. You will need library definitions for both golden and revised or else the set-up will be incomplete. The library cell and design code (e.g. verilog) need to match ports or else the design code is syntatically incorrect. If the cell is a ...
    Posted to Logic Design (Forum) by tstark on Wed, Feb 5 2014
  • Re: conformal -Lec (black boxing)
     The command is "add notranslate modules <module> -both". Use it before design library read-in. Often the term "black boxing" means using "add notranslate modules"  It is useful for memories, analog circuits, and "non-synthesizeable" code. If you don't "add notranslate module" ...
    Posted to Logic Design (Forum) by tstark on Tue, Jan 28 2014
  • Re: Conformal- LEC
    Make sure to use "write hier_compare dofile -run_hier" when running "run hier_compare". They work together. Also when using "run hier_compare" the hier dofile can't be edited. There are sample dofiles in the web interface:  SETUP/LEC> set web on   -ts
    Posted to Logic Design (Forum) by tstark on Fri, Jan 17 2014
  • Re: what is power switch and how they work in the design????
     A power switch gates a power or ground rail with an enable. It is used to turn-off power to gates (e.g. a block) for power savings. Typically power gates are inserted in P&R. There is a comprehesive tutorial here: http://www.powerforward.org/DesignGuide.aspx Power switches are now very common so I imagine there are many other tutorials ...
    Posted to Digital Implementation (Forum) by tstark on Mon, Oct 7 2013
  • Re: where can we get the RAK
    The RAK are available at http://support.cadence.com/raks. A Support account is required to access them. You can sign-up via the login page. If you need your hostID please contact your IT or Cadence AE. Note Safari and Chrome are not officially supported. I believe there is a small hurdle with Safari. It is possible there will be a problem ...
    Posted to Logic Design (Forum) by tstark on Tue, Sep 10 2013
  • Re: antenna diodes in LEC
    Unreachable points are points that don't reach an output pin and therefore don't affect a primary output logically. It appears the diodes don't matter in the functional compare of your design and can be ignored. I presume the design has no non-equivalents related to diodes. That is probably the best way do the compare. One option ...
    Posted to Digital Implementation (Forum) by tstark on Thu, Jun 20 2013
  • Re: Conformal LEC Dofile Arguments.
     I've wondered the same. The only way I know of is via shell environment variables.  $ setenv FOO bar  LEC  SETUP> echo $FOO  or  TCL_SETUP> puts $env(FOO)  A user made wrapper script around lec could provide this feature too. -ts
    Posted to Logic Design (Forum) by tstark on Thu, Jun 20 2013
  • Re: module naming with hexadecimal values
     LEC's renaming currently support decimal searches only. I imagine you could get creative and make a hex search but depending on your needs this could get difficult or impossible.   -ts
    Posted to Logic Design (Forum) by tstark on Mon, Apr 29 2013
Page 1 of 4 (34 items) 1 | 2 | 3 | 4 | Next >