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 Community Search 

Page 1 of 1 (4 items)
  • memory error
    Recently my design goes into the last stage. The simulation was very slow (lasting several days). Moreover, my simulation software crashed several times. I got the error messages below. (1). Unable to allocate memory for transition file slice variable transition index level (read). ERROR: Unable to allocate memory for reading transition file ...
    Posted to RF Design (Forum) by Andy Liu on Thu, Aug 6 2009
  • positive phase noise
    I simulated the phase noise of an LC VCO. The phase noise at very low offset is positive. For example, the phase noise is +13.2 dBc/Hz at 100 Hz offset whilst the phase noise at 1 MHz offset is -100 dBc/Hz. The carrier frequency is 5 GHz. Should phase noise be negative? If the component at 5.0000001 GHz is 13.2 dB larger than that at 5.0000000 ...
    Posted to RF Design (Forum) by Andy Liu on Thu, Jun 11 2009
  • half harmonic frequency in PSS analysis
    I am designing an LC based voltage control oscillator. I want to simulate phase noise of my oscillator, but, I ALWAYS got a very bad phase noise performance (for example, -60 dBc/Hz @ 1 MHz offset, compared to my expectation -110 dBc/Hz). The reason is that in the periodic steady state analysis (PSS), the fundamental frequency is simulated wrong. ...
    Posted to Custom IC Design (Forum) by Andy Liu on Thu, Apr 30 2009
  • half harmonic frequency in PSS analysis
    I am designing an LC based voltage control oscillator. I want to simulate phase noise of my oscillator, but, I ALWAYS got a very bad phase noise performance (for example, -60 dBc/Hz @ 1 MHz offset, compared to my expectation -110 dBc/Hz). The reason is that in the periodic steady state analysis (PSS), the fundamental frequency is simulated wrong. ...
    Posted to RF Design (Forum) by Andy Liu on Thu, Apr 30 2009
Page 1 of 1 (4 items)