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Page 1 of 63 (622 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »

DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7th year, IP Talks! includes over 30 half-hour live presentations and ...

Posted to Industry Insights (Weblog) by Richard Goering on Thu, May 16 2013
DAC 2013: User Perspectives on System-Level Verification
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference (DAC 2013) Tuesday, June 4 from 8:00 am to 10:00 am. The ...

Posted to Industry Insights (Weblog) by Richard Goering on Wed, May 15 2013
A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this convergence - and he wants to see better ...

Posted to Industry Insights (Weblog) by Richard Goering on Mon, May 13 2013
Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story
There is no doubt that Joe Costello, the first Cadence CEO, knows how to tell a compelling company story. Under his charismatic leadership, Cadence experienced explosive growth after its formation in 1988, becoming the largest EDA company within just a few years. It is thus fitting that the EDA Consortium (EDAC) invited Costello to speak as part ...

Posted to Industry Insights (Weblog) by Richard Goering on Sun, May 5 2013
Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation March 12, 2013, given by Jack Benzel (right), expert engineer at Avago Technologies. Avago, which ...

Posted to Industry Insights (Weblog) by Richard Goering on Wed, May 1 2013
EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to parasitic extraction. FinFET extraction challenges received a thorough review at the recent ...

Posted to Industry Insights (Weblog) by Richard Goering on Mon, Apr 29 2013
GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture at GLOBALFOUNDRIES. At the recent CDNLive Silicon Valley 2013 conference, Kye made the ...

Posted to Industry Insights (Weblog) by Richard Goering on Mon, Apr 29 2013
Cadence DAC 2013 and Denali Party Update
A very special Design Automation Conference (DAC) will take place in early June - it's the 50th anniversary of this conference, which has long been a focal point of the EDA industry. This year Cadence is celebrating its 25th anniversary and has considerable involvement in DAC 2013, including technology sessions, customer/partner presentations, ...

Posted to Industry Insights (Weblog) by Richard Goering on Thu, Apr 25 2013
Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment
3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good reflection of the tone of the panel, where ...

Posted to Industry Insights (Weblog) by Richard Goering on Tue, Apr 23 2013
Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack, but typically not for applications development. There is no magic tool that will fully ...

Posted to Industry Insights (Weblog) by Richard Goering on Sun, Apr 21 2013

Page 1 of 63 (622 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »

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