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 Community Search 

Page 1 of 1 (2 items)
  • LEC and Designware components
    Any method to resolve a blackboxed designware component on RTL netlist which does not match up to GATE level netlist?  Due to scan insertion on the DW_ram* module in gate leve netlist, LEC will not allow me to match up blackboxes between the golden and revised netlists. Any help on this one?  I can see if I have a sythesizable model ...
    Posted to Logic Design (Forum) by jlang on Fri, Aug 17 2012
  • IRUN and PlusArgs
    I am having issues trying to pass a $plus$args using IRUN.  Anyone have any clues?  Can we NOT use the +plusarg on irun command line?    ------------------------------ irun command line: **   irun -file simopts/rtl_opts.def -file chipfiles/chip_rtl.h -file chipfiles/chip_tb.h -top test -input ...
Page 1 of 1 (2 items)