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 Community Search 

Page 1 of 3 (21 items) 1 | 2 | 3 | Next >
  • Define via structure
    Hi all,          there is just explanation from Cadence Help about how can we use define via structure to duplicate via and cline we use frequently to do BGA fanout but there is no instruction on how do we able to delete those unused via structure? Does anyone over here know how to delete off those ...
    Posted to PCB Design (Forum) by ahkuih on Mon, Mar 18 2013
  • Re: RE: autosilkUtils.il
    Hi Dave,        now i am using your skill to check is there any silkscreen outside of board file, but keep running on few boards also complaining all placed component silkscreen outside of board outline. I have no idea. I just use default setting. I thought from your help file, it states that it reports red DRC if ...
    Posted to PCB SKILL (Forum) by ahkuih on Mon, Mar 11 2013
  • Re: RE: autosilkUtils.il
    hi Dave,      I download your skill code and unzip it into my usual skill folder which is c:\skill and then load it inside allegro PCB editor which is load"c:/skill/autosilktUtils_public.il". Then exit skill intepreter. Type silkutils but always encounter wrong command. May I know what should i do? I also followed ...
    Posted to PCB SKILL (Forum) by ahkuih on Mon, Mar 11 2013
  • Re: Overlap dynamic shape
    Hi Steve,           I don't think you get what I mean. Inside my board, there was no out of date shape. Due to multiple times of copper pour of dynamic shape type and also the breakout shapes from large shape were sticked to the board by the via. Duplicate shapes happen at the same location. I ...
    Posted to PCB Design (Forum) by ahkuih on Thu, Mar 7 2013
  • Overlap dynamic shape
    hi all,         I have a problem with overlap dynamic shape which was due to multiple copper pour on top side of my board. Due to this problem, whenever I try to generate top layer artwork, it will prompts me to delete off the shapes. The quantity of the overlap dynamic shape was too many until I was ...
    Posted to PCB Design (Forum) by ahkuih on Thu, Mar 7 2013
  • Global Routing Environment vs Autorouter
    Hi all,  does anyone have experience on using GRE , is it easier and more options for us to route complex traces versus autorouter? Which one is easier to pick up?
    Posted to PCB Design (Forum) by ahkuih on Thu, Feb 2 2012
  • Re: RE: DFA
    Hi George,                  Do you mind to clarify what do you mean with “working on beating it into shape” and what does it mean “ translating the Valor ERFs into the DFA tables”?
    Posted to PCB Design (Forum) by ahkuih on Mon, Jun 13 2011
  • DFA
    Hi,      I know that we can group our board component into class-based hierarchy so that it will be more organized. But i still in struggle what are the groups and how many groups i should created in order to cateogorize thousand of components in my library. Anyone mind to share with me how was the .dfa ?
    Posted to PCB Design (Forum) by ahkuih on Mon, Jun 13 2011
  • Re: RE: switch the release (14.2-15.7-16.0 and vice versa) error?
    i also used microsoft SETX command but I cannot switch to different version due to PATH setting there. I used batch file to control but failed. Can help to advise or not? Here is my batch file setting echo Setting environment for Cadence 16.2 cmd /c setx CDSROOT C:\Cadence\SPB_16.2 -m cmd /c setx CDS_INST_DIR C:\Cadence\SPB_16.2 -m cmd /c setx ...
    Posted to PCB Design (Forum) by ahkuih on Thu, Aug 20 2009
  • How to use Cadence SPB Switch Release
    Hi all,         I found difficulty in switching PCB Editor to different version when dealing with board saved under different version. For my current practice, I have to manually change my environment variable setting manually by using batch file to automate some of the setting like CDSROOT, HOME, CDSVER etc. ...
    Posted to PCB Design (Forum) by ahkuih on Thu, Aug 20 2009
Page 1 of 3 (21 items) 1 | 2 | 3 | Next >