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 Community Search 

Page 1 of 3 (23 items) 1 | 2 | 3 | Next >
  • Tap Insertion
    Is there any command on Encounter to insert tap cell arrays before placement to ensure that the placement complies with the maximum diffusion-to-tap limit?  
    Posted to Digital Implementation (Forum) by tswong on Mon, Jan 21 2013
  • Antenna check at Virtuoso Cadence Assembly Router
    Could anyone advise the steps to define and run the antenna checks at VCAR during the global routing? Regards, TS
    Posted to Custom IC Design (Forum) by tswong on Sun, Aug 7 2011
  • SDF Errors
    We are performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog ...
    Posted to Digital Implementation (Forum) by tswong on Mon, Jul 25 2011
  • Failed to find SETUP/HOLD timingcheck
    I am performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog ...
    Posted to Functional Verification (Forum) by tswong on Mon, Jul 25 2011
  • Missing Vias from VCAR
    Hi, all I found some vias of the pre-routed nets was lost after the routed database from VCAR was imported back to virtuoso layout editor. I double checked on VCAR and they are existed during the “exporting to router”, but some of them are gone during the “importing to router”. Does anyone have any idea of this? Regards, ...
    Posted to Custom IC Design (Forum) by tswong on Mon, May 10 2010
  • Re: Spacing for IO pins
    Alex, I can respace the pin spacings now. Thanks! Regards, TS  
    Posted to Custom IC Design (Forum) by tswong on Thu, Mar 4 2010
  • Re: CMX Error
    Quek, I can find the constraint insdie the CM as you said, but I cannot remove it. It returns with message "Read-only constraints will not be deleted"  Do you know how to fix it? Regards, TS
    Posted to Custom IC Design (Forum) by tswong on Thu, Mar 4 2010
  • Re: Spacing for IO pins
    Alex,  Thanks for you reply!  Actually my module is small, but with high pin counts. It is very time consuming to move in manually. By the way, could you say more about the "Respace" feature and where I can find it....  Regards, TS
    Posted to Custom IC Design (Forum) by tswong on Wed, Mar 3 2010
  • Spacing for IO pins
    Does anyone know how to set the absolute spacing of I/O pins when doing the I/O place inside the PREVIEW?  Can I set the value on I/O constraint file? 
    Posted to Custom IC Design (Forum) by tswong on Wed, Mar 3 2010
  • CMX Error
    I received the following errors when I opened the autolayout view of amodule. Does anyone know about it? CMX ERROR: constraint [lxVcpBoundary0]: invalid pin name [CTL7<0>|CTL7<0>] CMX ERROR: constraint [lxVcpBoundary0]: members not resolved I checked the pin CTL7<0> and cannot find the name as reported.
    Posted to Custom IC Design (Forum) by tswong on Wed, Mar 3 2010
Page 1 of 3 (23 items) 1 | 2 | 3 | Next >