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 Community Search 

Page 1 of 2 (16 items) 1 | 2 | Next >
  • Cant we randomize a string variable?
    All,   I tried randomizing a string ,first i defined a class in which i have one of the random variables of type string,then i used constraints to fix the value of the string ,however i got a compilation error which says randomizing strings is unsupported.Has anyone tried randomizing strings ? Do we really need to randomize them (I just ...
    Posted to Functional Verification (Forum) by hipooja on Tue, Nov 24 2009
  • How/Where/when to use unions
    I understand union to be a user defined data type that can store variables of different data types,however unlike class they do not contain methods to operate on the properties and they occupy the same memory as the largest data in them. I however do not know How ,when ,where and why to use unions as i have used classes extensively but not tried ...
    Posted to Functional Verification (Forum) by hipooja on Mon, Nov 23 2009
  • Why do we code FF using NBA w.r.t Stratified event queue
    Hello,   i was looking at the Verilog/Sysverilog stratified event queue and had a question as to why FF are coded using NBA? I came up with an answer myself ,just wanted to cross check whether i hit / missed the bull's eye ... FF are basically memory elements and hence must store value They sample the previous ,stable outputs -The ...
    Posted to Functional Verification (Forum) by hipooja on Mon, Nov 23 2009
  • Re: Clocking blocks /cycle based sampling and driving
    I figured out that modports are the first step to reusability ,suppose there is a master and slave wherein only the direction of signal is different,then all you need to do is bunch the signals and define directions in modport and pass the modport to the constructor of the master and slave module,hence it spares the effort of defining the signals ...
    Posted to Functional Verification (Forum) by hipooja on Fri, Nov 20 2009
  • Re: unique and priority in SV
     Thanks Shalom and Vinay,   I am now pretty certain that priority keyword infers a priority mux (which happens even without the 'priority' keyword) and it the advantage of using priority is that it issues a run-time warning if all the cases are not covered   Thanks, Pooja
    Posted to Functional Verification (Forum) by hipooja on Fri, Nov 20 2009
  • Re: Ref to variables
    Hi,   I do not think you can pass a variable which is not defined in the class ,to its method.This is because the class must know beforehand the type of the variable (I think)   For example when you pass the channel handle to the constructor of the driver ,you need to define the channel handle before utilizing it.Oki let me put up a ...
    Posted to Functional Verification (Forum) by hipooja on Thu, Nov 5 2009
  • Re: Clocking blocks /cycle based sampling and driving
    I also read that clocking blocks seperate signal functionality and timing and help avoid user induced races.The latter point i understand is because clocking blocks samples the signal x time before the sampling event and holds the signal y time after the sampling event ,which avoids metastability and hence X's,the former point is however ...
    Posted to Functional Verification (Forum) by hipooja on Wed, Nov 4 2009
  • Re: RE: Difference : Semaphores and Mailboxes
    Thanks Tim,   So in a nutshell semaphores are used to avoid bus contention when two drivers drive the same bus or allow a process to read a register ,only when it has been written to.Mailboxes as you mentioned can be used to send data between concurrent process such as generator and driver and can configured for WAIT,NO_WAIT.......and the ...
    Posted to Functional Verification (Forum) by hipooja on Wed, Nov 4 2009
  • Re: RE: Active/Reactive regions
    Tim, Does'nt the Reactive region come into picture after the blocking and non-blocking assignments have been done in the stratified event queue? I understand that the reactive region comes after the active region and programs work in the reactive region of the queue so that by that time all blocking ,non-blocking and continous assignments ...
    Posted to Functional Verification (Forum) by hipooja on Wed, Nov 4 2009
  • Re: Components of System verilog VE
    Hi , A TB essentially consists of the following 1.DUT instance 2.Clock generator for the DUT using always block or forever loop statement 3.Reset generation mechanism 4.Local wires and reg declaration to drive clock ,reset and connect the DUT to the testbench since the testcase instantiates the TB and the medium to access the DUT is through ...
    Posted to Functional Verification (Forum) by hipooja on Wed, Nov 4 2009
Page 1 of 2 (16 items) 1 | 2 | Next >