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 Community Search 

Page 1 of 1 (4 items)
  • Hold violation at post P&R simulation
    Hello,  I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean ...
    Posted to Functional Verification Shared Code (Forum) by shahein on Sun, Oct 7 2012
  • How to Simulate 64-bit VHDL Code in Cadence?
    I am trying to simulate a VHDL code which have internally values exceeds the range of (-2**31 to 2**31). However, I can synthesize the code but I can't simulate it.  I tried to change the attribute  set intovf_severity_level IGNORE but it didn't work as well. I would appreciate your suggestions.  Regards.
    Posted to Logic Design (Forum) by shahein on Tue, Sep 4 2012
  • Synthsis of VHDL-2008 on RC
    Dear All,  I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly.  However, I am not able to synthesis the same code using RC. I am using Cadence 5 flow with RC v10.1. What is your recommendations to overcome this issue. In waiting for your ...
    Posted to Digital Implementation (Forum) by shahein on Thu, Jul 26 2012
  • Protected Data Types by VHDL 2008
    I am trying to compile some VHDL files which contains a protected data type. I am using Cadence 10.2. I set the library path to the Incisive library path, i.e., $IUSHOME/tools/inca/files. In this folder I check the csd.lib file and the IEEE proposed library. The library is already compiled at the IEEE folder, e.g., ...
    Posted to Functional Verification (Forum) by shahein on Mon, May 14 2012
Page 1 of 1 (4 items)