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Page 1 of 2 (20 items) 1 | 2 | Next >

Creating SystemC TLM-2.0 Peripheral Models
Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time to give you an update, and the good news is that such a tool is now available as part of the new ...

Posted to System Design and Verification (Weblog) by Team ESL on Thu, Jul 14 2011
Understanding Latency versus Throughput
One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated. Suddenly, both "Systems designers" and "Hardware designers" are using not only the same input language to ...

Posted to System Design and Verification (Weblog) by Team ESL on Mon, Sep 13 2010
More Details on Post Silicon Embedded Software Verification With ISX
Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in Germany, to the TeamESL blog for the next installment on post-silicon embedded software verification with ISX. This post is a discussion featuring Markus and Joerg talking to Malte Henzelmann and Ernst Zwingenberger of El Camino GmbH. It builds on ...

Posted to System Design and Verification (Weblog) by Team ESL on Tue, Aug 18 2009
A Classification of ESL - High Level Synthesis Tools
These days, there is a lot of talk of what the next design methodology for Digital Systems will be and how this methodology will be the replacement of RTL Synthesis. The term ESL (Electronic System Level) is used as a general term for the new wave of modeling and synthesis for digital systems. We have noticed that the term ESL is a very ...

Posted to System Design and Verification (Weblog) by Team ESL on Thu, Aug 6 2009
Full System vs Sub-system Virtual Prototyping
There is a strong movement in the industry to move to create Virtual Prototypes of systems, prior to RTL coding. These Virtual Prototypes are being used for early software development and architectural analysis. Since there are typically many blocks in a design, the development of a Virtual Prototype can be unwieldy. While you might have a goal of ...

Posted to System Design and Verification (Weblog) by Team ESL on Thu, Aug 6 2009
Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle?
Being a Brit, Cricket is never very far from my thoughts especially when travelling to India, the biggest cricket mad nation in the world. There is a saying in cricket that you should always think of doing what the opposition would least like, a statement that applies in business too. I was on my way to present a session on Verifying Embedded SW ...

Posted to System Design and Verification (Weblog) by Team ESL on Wed, Aug 5 2009
Customer Questions About TLM-driven Design and Verification
In the latest blog published by Ron Wilson there were two questions about our TLM-driven design and verification solution introduction. We would like to respond to these comments here: 1. "one line of SystemC generates three lines of RTL" During our interview with Ron, we showed an example of one of our customers who ...

Posted to System Design and Verification (Weblog) by Team ESL on Mon, Jul 27 2009
OVM Metric Driven Verification With an FPGA-based Design
During the last 2 years I have enjoyed the opportunity to work with the Incisive Software Extensions (ISX) with many customers. I learned a lot about software/hardware co-verification and we reached the point were we started to see beyond one’s own nose. One of the substantial concepts of ISX is the generic software adapter. The ...

Posted to System Design and Verification (Weblog) by Team ESL on Wed, Jun 17 2009
Way Worse Than The Real Thing
This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual platforms make it possible to test software in ways that are plain impossible on physical ...

Posted to System Design and Verification (Weblog) by Team ESL on Mon, May 18 2009
SystemC Debug: A Summary of Summary Probes
SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in order to represent concurrent systems, whether for modeling a system-on-chip, or creating a ...

Posted to System Design and Verification (Weblog) by Team ESL on Fri, May 15 2009

Page 1 of 2 (20 items) 1 | 2 | Next >

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