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 Community Search 

Page 1 of 1 (5 items)
  • ncvhdl compilation error
      Normal 0 false false false EN-GB X-NONE X-NONE MicrosoftInternetExplorer4 ...
    Posted to Digital Implementation (Forum) by livid on Fri, Jul 18 2014
  • use of nc_force, nc_release in a clocked process in the TB
     Hello   I wondered if it is possible to use nc_force, nc_release in a clocked process in the test bench.   for example, the code i was thinking of was;   process (clk) begin     if(test_bench_signal = '1'I then          nc_force("destination, value);     ...
  • nc_mirror
     Hello   The SOC Test chip we are designing has numerous embedded RAMs. We use an on-chip BIST controller for testing the RAMs.   Currently i am trying to test one of the RAMs by simulating a s-a-{0,1} fault.  Previously we did this using the force command from ncsimrc file. However, i was given a recommendation that i ...
  • Code Coverage with ICCR
     Hello   I am using ICCR 10.20-s043 in the gui mode to view the coverage data that i have generated for a sub-block embedded deep in the top level design.   In the ICCR gui mode, i can view the coverage for each instance and the cummulative total. The problem i am having is how to generate this view as a text file ...
    Posted to Functional Verification (Forum) by livid on Thu, Jul 28 2011
  • Assertions
    Hello   I am just embarking on our groups ABV strategy. We use VHDL for our IP development.   Currently, after a few iterations, we are going down the PSL assertion approach (as opposed to the System Verilog Assertion (SVA)) for embedding assertions at the sub-block level.   My understanding was that PSL is HDL language ...
    Posted to Functional Verification (Forum) by livid on Thu, Jul 21 2011
Page 1 of 1 (5 items)