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 Community Search 

Page 1 of 1 (5 items)
  • Re: Generating .lib file from layout
    Automated is a tall order for a custom cell; however, you should review the Virtuoso Foundation IP Characterization datasheet:  http://www.cadence.com/rl/Resources/datasheets/Virtuoso_Foundation_IP_Characterization.pdf This technology was acquired from Altos and has replaced DCM in ICADV12.1. It is a more automated approach for library ...
    Posted to Custom IC Design (Forum) by mariek on Tue, May 7 2013
  • Re: Layout: from Encounter to Virtuoso
    Hi Francesco,  1) The OA netlist field is used only when an existing cellView contains the netlist information. This could be done with a cellView which was created with VLS-XL or with Encounter.  Most designs start with a Verilog netlist.  2) The lib.defs must be in your working directory: "encounter".  ...
    Posted to Custom IC Design (Forum) by mariek on Wed, Aug 5 2009
  • Re: Layout: from Encounter to Virtuoso
    Hi Francesco, The preferred method for exporting a database from Encounter to Virtuoso is through the use of OpenAccess (IC 6.1.3) or DEF (IC 5.1.41 and DEF 5.5). This will resolve your layer mapping issues and will retain the connectivity information in the database.  The resulting cellView may be modified with VCE and returned to ...
    Posted to Custom IC Design (Forum) by mariek on Tue, Aug 4 2009
  • Re: HDL to Layout
    Hi Dennis, Translation from HDL to layout requires logic synthesis to map to from C, behavioral or RTL constructs to a target technology library. Digital physical implementation is then used to map a gate-level netlist to layout using optimizations for area, timing, and power. For synthesis, you may find this reference useful: ...
    Posted to Custom IC Design (Forum) by mariek on Thu, Jul 16 2009
  • Re: Generating .lib file from layout
    Hi Raj, Depending upon the functionality of your layout, there are several options for creating a dotlib.  1) Encounter LIbrary Chracterization is part of the Encounter Timing System and useful for digital std_cells and I/Os. http://www.cadence.com/rl/Resources/datasheets/library_characterizer_ds.pdf 2) Spectre MDL is a flexible solution ...
    Posted to Custom IC Design (Forum) by mariek on Thu, Jul 16 2009
Page 1 of 1 (5 items)