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 Community Search 

Page 1 of 3 (26 items) 1 | 2 | 3 | Next >
  • How-to Plans for ECOs - Advice From Experts
    By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or, what is the impact of RTL coding style, aggressive design optimization, and hierarchy ungrouping ...
    Posted to Logic Design (Weblog) by Team FED on Thu, Oct 15 2009
  • Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
    By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs), designs are getting more congested. The normal approach to solve congestion has ...
    Posted to Logic Design (Weblog) by Team FED on Tue, Aug 11 2009
  • Do You Also Need to be a DFT, STA, Verification, Low-Power, and Library Expert? Not Anymore!
    By Jack Marshall Sr. Tech Leader, Solutions Our R&D team has just released a major new feature in RTL Compiler 9.1.100.  It is called "Quality Analyzer".  I call it "RC QA" for short - since that's how you invoke the feature (rc -qa).  It's our first attempt at producing an integrated, ...
    Posted to Logic Design (Weblog) by Team FED on Tue, Aug 4 2009
  • RTL Compiler's New "Spatial Technology"
    By Jeff Flieder Sr. Solutions Manager Over the last few years, RTL Compiler has added a significant number of features targeted toward users that require more physical awareness in their synthesis flow. We first introduced the PLE (Physical Layout Estimation) flow that allows a very low impact way to accurately model 80-90% of the wires in ...
    Posted to Logic Design (Weblog) by Team FED on Tue, Jul 28 2009
  • DesignWare and AmbitWare Demystified - Why and When to Avoid?
    By Diego Hammerschlag Sr. Technical Leader Team FED  Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware being that many of ...
    Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
  • RC Design Explorer: Find the Right Balance of Power and Performance
    By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them.  Lowering voltage levels can be a great way to reduce switching power, but it comes at the cost of reducing performance.  As we have talked to ...
    Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
  • How to Pick a Synthesis Tool - The Right One for You - Part 2
    By Kenneth Chang, Core Comp AE, Team FED. In my previous blog, I had written about how "Synthesis matters."  Snippet below. <snip> I had a boss that once said that all synthesis tools are same.  This guy knew his stuff, been in the industry forever.  He said "synthesizing with Tool X may give ...
    Posted to Logic Design (Weblog) by Team FED on Tue, Jul 7 2009
  • Free Online Training: Conformal LEC
    By Kenneth Chang Core Comp AE Team FED.    If you didn't know, Conformal's very own AE team put together some cool training materials for their customers based on large demand to help both new and intermediate users. It's free.  And it's personal with Clay and Bruce.  You may have even worked with ...
    Posted to Logic Design (Weblog) by Team FED on Mon, Jun 22 2009
  • Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate
    By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not careful. Such methodology decision can impact:Quality of Silicon (QoS)Equivalency ...
    Posted to Logic Design (Weblog) by Team FED on Mon, Jun 22 2009
  • Low Power Guide from Industry Leaders
    By Kenneth Chang, Core Comp AE, Frontend Solutions.  Low power concerns continue to drive companies' needs for optimized ASIC methodologies, which is why one of the Si2 key initiatives continues to be the standardization of Low Power Intent. Below is just a couple of snapshots of posters which show the ...
    Posted to Logic Design (Weblog) by Team FED on Thu, May 28 2009
Page 1 of 3 (26 items) 1 | 2 | 3 | Next >