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# Community Search

Page 1 of 5 (41 items) 1 | 2 | 3 | 4 | 5 | Next >
• Re: PN function in Visualizaion & Anaysis XL Calculator
Hi JaeWook, The December 2012 ViVa reference manual describes the pn() function as follows: "Returns a waveform for the transient phase noise of the input waveforms in decibels (dBc/Hz). Phase noise is defined as the power spectral density of the absolute jitter of an inputwaveform." Hence, as Andrew mentions, it is not the classical ...
Posted to RF Design (Forum) by smlogan on Tue, Feb 18 2014
• Re: How to measure AC differential output results using calculator?
Hi xxgenerall,  > How could i measure the output differential signal with the calculator?  You have not provided your circuit, so I do not know where /net28 and /net36 are in your circuit.  >  is it correct for both gain and phase?  In general, you measure the output as the difference between the ...
Posted to RF Design (Forum) by smlogan on Wed, Dec 4 2013
• Re: How to calculate THD using calculator?
The THD, as a parameter, is defined as the rms sum of all the fundamentally related harmonics in a signal. Hence, the function, I believe, computes the total harmonic distortion in a manner consistent with the definition (given the FFT length). To compute the harmonic distortion for a lesser number of harmonics or over a particular frequency ...
Posted to Custom IC Design (Forum) by smlogan on Tue, Dec 3 2013
• Re: how to plot capacitance vs voltage in cadence virtuoso
Yes. You can get a plot similar to whata you show from ADS.  For the small signal capacitance, apply an AC current source between  the two terminals of your capacitive elements and monitor the voltage across them in a small-signal AC simulation. To feed a DC voltage across the terminals, use a large (ideal) inductor whose ...
Posted to RF Design (Forum) by smlogan on Mon, Dec 2 2013
• Re: how to plot capacitance vs voltage in cadence virtuoso
Hi Venkateshjutur, You will need to create a test bench with your varactor structure, switches and whatever layout parasitic elements are involved. You can excite the entire structure from the terminals that the inductor would be looking into with a DC voltage (possibly isolated with a very large indicator) and deterrmine the resulting small ...
Posted to RF Design (Forum) by smlogan on Tue, Nov 26 2013
• Re: harmonic balance oscillator
Dear kpti, I believe the issue is that in your your pss simulation result, there is no oscillation in the steady-state. The resonator you are illustrating shows a resistance of 50 ohms I believe provides the possible solution of damping out any steady-state oscillation. Hence with time, a steady-state solution consists of a DC voltage across ...
Posted to RF Design (Forum) by smlogan on Sat, Nov 23 2013
• Re: Phase noise of frequency multiplier
Hi MTP3,   Thank you for your detailed update! [1] - Great - this a good thing! [2] - I've never needed to use anything less than a maxstep of 1/100 of the period of interest for stiff oscillators in pss in the MHz range. Hence, I suspect with your 2 GHz design a maxstep value of 1/100 is more than sufficient. Perhaps you might ...
Posted to RF Design (Forum) by smlogan on Tue, Nov 19 2013
• Re: Phase noise of frequency multiplier
Hi MTB,   A couple of thoughts came to mind - perhaps you have already explored these. 1. Are all three ring oscillators operating at exactly 2 GHz? The concern is that if they are not, one of the intermodulation products may have a very low relative frequency (i.e., for example 2 GHz/1.999 GHz => 0.001 GHz) which could make pss ...
Posted to RF Design (Forum) by smlogan on Mon, Nov 18 2013
• Re: Changing font and size of A/B and Delta Markers with SKILL