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 Community Search 

Page 1 of 2 (11 items) 1 | 2 | Next >
  • Re: interconnect check with PSL
    Hi BJ,  The problem you face is likely how to specify out-of-module references. This can be done with nc_mirrors. This way you can "bind" to one entity but see any entity/module signal via the mirror call.  That said, I did want to mention that Cadence has a pre-packaged verification app that addresses this problem directly. ...
    Posted to Functional Verification (Forum) by ckomar on Wed, Oct 23 2013
  • Re: Formal Verification with SystemVerilog and ifv
    Hi,  Complexity can often be addressed with methodology and tool capabilities. But this is a large topic that will be difficult to discuss using this forum. I can suggest a couple of things 1) view an older post in which document was posted on how to improve performance http://www.cadence.com/community/forums/T/26285.aspx  2) discuss ...
    Posted to Functional Verification (Forum) by ckomar on Wed, Jul 31 2013
  • Re: Engine for IFV
    Hi Buvna,  This is probably less likely about engine and more about tool version and running in parallel.  Are you using the latest 12.2 software?  In more recent versions there have been optimizations on running the automatic checks.  In addition are you running your job with parallel distribution? This is the most effective ...
    Posted to Functional Verification (Forum) by ckomar on Thu, Jun 6 2013
  • Re: SOC connectivity check
    Hi Buvna,  Best thing to do is to go through the training material that is shipped with the tool. The training materials can be found at:  <install>/doc/kit_topics/abv/workshop/IFV_Connectivity_Training.pdf  With associated lab material ...
    Posted to Functional Verification (Forum) by ckomar on Tue, Jun 4 2013
  • Re: uninitialized state elements
    Hi Bharath,  Could be a number of reasons that the state elements are not initialized. To figure out which elements are uninitialized you can do "init -show". If you want to debug why they are not being initialized you can do "debug -init". This will bring up an empty waveform window that you can add whatever signals you ...
    Posted to Functional Verification (Forum) by ckomar on Mon, May 27 2013
  • Re: IFV Dead code check fail
    The meaning of a failing deadcode check is that line of code is unreachable.  Meaning no matter how the inputs are exercised, given the DUTinitial state you provided the tool of the DUTany constraints you might have appliedthere is no possible way to reach that code. In terms of understanding this more and debugging these, I strongly ...
    Posted to Functional Verification (Forum) by ckomar on Mon, May 20 2013
  • Re: Profiling the runtime of SystemVerilog Assertions
    Hi Daniel,  You are correct. This feature was added in version 8.2. I just tried it on a simple testcase that I have and get the following in my ncprof.out.  Are you not seeing a section in the log file that looks something like this? ------------------------------------------------------------ Assertion Summary Counts (15 hits, 28.8% ...
    Posted to Functional Verification (Forum) by ckomar on Thu, Jan 15 2009
  • Re: System Verilog Assertions!!
    As Joerg states, contacting your local AE would be a good next step. We already have an AEware set of assertions for SPI that they would be able to share with you. This would be an excellent way to get jump started.  Chris
    Posted to Functional Verification (Forum) by ckomar on Thu, Dec 18 2008
  • Re: RE: RE: Verification Plan using Eplanner
    Hi Manish,   I also want to make sure you're using 8.2 software. This is the only version of Enterprise Manager that will enable you to see check status in the vPlan view. Thanks, Chris
    Posted to Functional Verification (Forum) by ckomar on Tue, Dec 9 2008
  • Re: Questions about IFV - PLS Help! - New to IFV
    Hi,  I would strongly encourage you to contact your local AE.  We have a training that will answer your questions. In addition, our training labs include an example that has an sop/eop protocol.  My guess is you'll be able to take those assertions from the lab, learn how/why they work and drop them into your design at the same ...
    Posted to Functional Verification (Forum) by ckomar on Wed, Dec 3 2008
Page 1 of 2 (11 items) 1 | 2 | Next >