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 Community Search 

Page 1 of 5 (50 items) 1 | 2 | 3 | 4 | 5 | Next >
  • Re: Allegro Design Entry HDL SKILL Copy Schematic Page
     Hi, if your purpose is to have same schematic in these pages, look at design reuse with hierarchical schematic. It can do this without writing a line of code...
    Posted to PCB SKILL (Forum) by jch teyssier on Thu, Oct 4 2012
  • Re: automatic silkscreen
     Hi, what kind of entity do you use for  silkscreen? Only lines can be "cut", not shapes
    Posted to PCB SKILL (Forum) by jch teyssier on Tue, Aug 21 2012
  • Re: Back annotate / Netlist Update
     Sound like the netlist was manually modified in allegro (edit logic): no other way to change footprint. When you attempt to modify logic in allegro, you get a warning and you have to set a variable in order to go ahead: no way to modify logic without be aware of that. In logic have be modified, there is no way to backannotate in schematic: ...
    Posted to PCB Design (Forum) by jch teyssier on Tue, Aug 21 2012
  • Re: Confused about copper pour spacing to hole
     Maybe it is not that, but there were an undocumented thing in older versions (maybe it s the same for 16.3 and 16.5?). If a via is a testpoint, then the constraint used is for test point, EVEN IF A GREATER SPACING VALUE is defined for this net for vias. Exemple: via/shape defined to 25 mils shape/testvia defined to 10 mils The value ...
    Posted to PCB Design (Forum) by jch teyssier on Wed, Jun 27 2012
  • Re: How to remove layers from existing stack-up?
     Hi Clint,   some things that can prevent of removing an etch layer: - Used in a artwork definition - Layer specific KEEP-out's present (exemple: a route keepout) - Database padstack with definition on this layer. -... several others, you have to find it  Do you run dbdoctor on your brd?   Jean-Charles
    Posted to PCB Design (Forum) by jch teyssier on Wed, Jun 27 2012
  • Re: REG: Straps in PCB
    I agree with Redwire: straps are jumpers for single sided pcb's.(it is the french term for this)
    Posted to PCB Design (Forum) by jch teyssier on Sun, Mar 6 2011
  • Re: Good Luck and Best Wishes to eDave
    Haven't heard about this earthquake...  Hope all will return to "normal" quickly for you and peoples around.  Jean-Charles
    Posted to PCB SKILL (Forum) by jch teyssier on Sun, Mar 6 2011
  • Re: Text block mapping
     Good day,  if text block definition defere between footprint and brd, then allegro try tu use one other text block with same definition. If not found, then it create a new text block and use it. Problem;  you never know which text block will be used and there is a limitation in number of text blocks: 64. When you reach this ...
    Posted to PCB Design (Forum) by jch teyssier on Tue, Dec 7 2010
  • Re: Difficulty updating pin count on existing schematic/pcb
     Well, allegro is driven by netlist. So it is regular to not be able to modify something if the result is not correct with the netlist. I prefer ths behavior to some behavoir "user frendly" but so dangerous...(some tools let user do what they want, really all, even if result is WRONG) Now, i agree that this point (and several ...
    Posted to PCB Design (Forum) by jch teyssier on Tue, Nov 23 2010
  • Re: Difficulty updating pin count on existing schematic/pcb
     You can not update symbol because it would be mismatched with the netlist. You can not update the netlist because it would be mismatched with actual symbol .   Right?  1) remove symbol from brd so it is forget. Import your netlist and place the component. (mu favorite, remenber coordonates/totaio/mirror if you wish it to be at ...
    Posted to PCB Design (Forum) by jch teyssier on Mon, Nov 22 2010
Page 1 of 5 (50 items) 1 | 2 | 3 | 4 | 5 | Next >