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 Community Search 

Page 1 of 1 (5 items)
  • Re: Scan mode and scan chain control from internal registers
    Sinjeet,   This gets into direct tool flow support.  What company do you work for?  Do you have a Cadence AE that you work with?     In summary if you want to see what a modeinit looks like, do the following in the ET GUI: - Pull up the GUI for the tbdata you are working with - Go to Report->Sequences.. - Load in ...
    Posted to Logic Design (Forum) by Andy Hughes on Thu, May 9 2013
  • Re: Scan mode and scan chain control from internal registers
    Sinjeet,  First, I am assuming that those control registers are not part of any of your normal ATPG chains, correct?  Also, from your description are you just setting internal values to change your PO's to proper outputs for your SO's?  Anything else this configuration does?  Any type of setup sequence like this would ...
    Posted to Logic Design (Forum) by Andy Hughes on Thu, May 9 2013
  • Re: "Word too long" error while running write_vectors step in Encounter test
    Krishnaraj,    Is there a reason you are using version 8.1.200 of our software?  We are releasing 11.1 in a couple of weeks which puts you 3 major releases behind.  There have been command, variable and character length issues in the past.  Most of those have been fixed.  Please try your design with a a more recent ...
    Posted to Logic Design (Forum) by Andy Hughes on Tue, Nov 1 2011
  • Re: TAP Control signals
     Insiya,     The control signals generated by the RTL-Compiler JTAG controller all conform to the 1149.1 standard.  All control signals are generated based on specific states and state transitions.  Clock-DR and Clock-IR clock pulses are generated during different states.  For instance, Clock-DR pulses are generated ...
    Posted to Logic Design (Forum) by Andy Hughes on Fri, Nov 13 2009
  • Re: User defined data registers in JTAG
     Insiya,      My first question would be, are you planning on implementing this jtag architecture on your own or are you using RTL Compiler to insert it for you?   Andy Hughes Core Comp Architect
    Posted to Logic Design (Forum) by Andy Hughes on Fri, Nov 13 2009
Page 1 of 1 (5 items)