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Page 1 of 3 (28 items) 1 | 2 | 3 | Next >
  • Re: FSM_NoDeadlock - Explored (IFV)
    Hi, from the IFV "Whats New": Updates to deadlock stateIn this release, the deadlock state property has been enhanced to check that the FSM cannot take any transition to the same state under any possible input combination. This deadlock state is supported by all engines and results in an improved performance. For complete ...
    Posted to Functional Verification (Forum) by JoergM on Mon, Jul 15 2013
  • Re: FSM_NoDeadlock - Explored (IFV)
    Hi, besides increasing the effort and partitioning the design there is not much you can do. Note that the FSM NoDeadlock check is a very complicated check that has to verify the FSM in context of all other state bits as well as excluding unfairness on all inputs. There is a change in FSM NoDeadlock checks starting in 13.1 that will improve ...
    Posted to Functional Verification (Forum) by JoergM on Sun, Jul 14 2013
  • Re: IFV run time errors
    Hi Pryia, The steps you describe are the setup of your tool environment. But I suspect that the underlying tool installation is incomplete. Please start our installation software iscape and repeat the configuration step. Jörg.  
    Posted to Functional Verification (Forum) by JoergM on Thu, Jul 11 2013
  • Re: IFV run time errors
    Hi, this looks like a installation configuration issue. I suspect you installed, but did not configure the Incisive installation. Please revisit the installation procedures and make sure you complete configuration. Thanks, Joerg
    Posted to Functional Verification (Forum) by JoergM on Tue, Jul 9 2013
  • Re: AFA for VHDL in IFV
    Hi, IFV support AFA in all HDL languages including VHDL, Verilog and SystemVerilog. What you experience is either a setup or a tool problem. Jörg.
    Posted to Functional Verification (Forum) by JoergM on Mon, Jun 24 2013
  • Re: how to reduce explored
    Hi Barath, I attach an app note that summarizes tool options to improve results. This can not replace review and optimization of your property and environment. If you need more help please contact your local Cadence AE. Regards, Joerg.
    Posted to Functional Verification (Forum) by JoergM on Wed, May 22 2013
  • Re: IFV assertion check problem
    Hi, 1. The property probably does not have a trigger, like "assert never {a && b}" - can you confirm that? 2. In order to get the trace you need to add "define witness auto" or "define witness trace" before the prove command Jörg.
    Posted to Functional Verification (Forum) by JoergM on Tue, Jan 22 2013
  • Re: Need help in assertion based connectivity checking
    Hi Snehal, I would like to add that in the next release 13.1 we will add covers to the connectivity checks that make sure we do not validate a stuck connection. Thanks again for your query. Jörg.
    Posted to Functional Verification (Forum) by JoergM on Mon, Jan 7 2013
  • Re: Need help in assertion based connectivity checking
    Hi Snehal, you need to add "+enable_togglecheck" to the iev commandline in order to infer the automatic toggle checks. please refer to chapter 10 of the Formal Verifier User Guide for details on "Toggle Checks". Jörg.
    Posted to Functional Verification (Forum) by JoergM on Thu, Jan 3 2013
  • Re: Need help in assertion based connectivity checking
    Hi Snehal, 1) IEV verifies the connection using all possible values within one single proof. The witness you see when opening the waveform browser is only 1 example of a scenario that fulfils the property. You can assume that the fomal engine considers all values, not only the one displayed in the witness example waveform. There is one caveat: ...
    Posted to Functional Verification (Forum) by JoergM on Wed, Jan 2 2013
Page 1 of 3 (28 items) 1 | 2 | 3 | Next >