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# Community Search

Page 1 of 10 (96 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
• Re: DC-DC Converter/ Feedback/ Verilog-A
Well, of course because I want to compare the result of your TRAN analysis with the VSIN source at 100 MHz with the result of your PAC analysis. The phase seems to match pretty well: the TRAN analysis gives approximately 0 degrees and the PAC analysis gives 3.8 degrees. The amplitude does not match quite as well: the TRAN analysis gives ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Fri, Aug 22 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
I want you to read out the value at 100 MHz in your plot http://postimg.org/image/f4rzrjzx1/ (if this simulation was done with the same circuit as your recent one). In this simulation, there was no 100 MHz sine, remember? When you were reading out the DC values at the output, you were taking the mean value of the ripple, remember? So you ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Thu, Aug 21 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
Well, a phase of 180 degrees at DC means that your linear gain at DC is not +2.418 but -2.418. This means that if you increase the input voltage by 10 mV, the output voltage will not increase but decrease by 24.18 mV, just as you have observed. Your simulation with the VSIN source shows a phase of approximately 0 degrees and a linear gain of a ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Thu, Aug 21 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
I am happy to see that your results for the DC gain match the PAC results very well. Regarding your "issue": Please think about what a phase of 180 degrees at DC means. You can either insert a VSIN source in series with the VDC source or replace the VDC source by a VSIN source and set the DC value of the VSIN source correctly (and also ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Wed, Aug 20 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
You can easily verify the DC gain. Increase the value of the DC source at the input by a small amount (1 mV or 10 mV, for example) and observe how much the output voltage changes due to this. Check if this ratio corresponds to the low-frequency gain that you have simulated (8 dB or so according to your plot). In principle, you can also do this at ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Wed, Aug 20 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
I believe that your simulation setup is correct. The fact that you do not see peaking is probably due to losses in your circuit. By the way, using a voltage-limited vcvs as the comparator was a good choice as it avoids the problem described in http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426.
Posted to Custom IC Design (Forum) by Frank Wiedmann on Wed, Aug 20 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
The number of sidebands should not matter, you can use 0. Why should you put your PAC source at the input of the modulator block? Because the simulation result is rather difficult to interpret if you apply the PAC source at a node of your circuit where you have a modulated signal. Think for yourself: What is the effect of adding a sinewave to the ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Tue, Aug 19 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
I suggest that you put your PAC source at a node of your circuit where you have an unmodulated signal. This would mean that you include the circuit that converts a DC voltage to the duty cycle of the converter. Put a DC source with the correct voltage at its input and set its PAC magnitude to 1. Make sure that in your netlist, the PSS analysis ...
Posted to Custom IC Design (Forum) by Frank Wiedmann on Tue, Aug 19 2014
• Re: DC-DC Converter/ Feedback/ Verilog-A
Connect the PAC source between ground and the input of the circuit that you want to examine (and add a DC value so that the input node will be biased correctly).
Posted to Custom IC Design (Forum) by Frank Wiedmann on Fri, Aug 15 2014
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