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 Community Search 

Page 1 of 1 (9 items)
  • Re: pin placement around core in encounter
    Hi, You can use editPin command in way to place IO pins on boundary of the block. Just example from documentation (Encounter Digital Implementation System Text Command Reference): Example: The following command modifies the pins as specified here: - the command runs on the module DTMF_CORE_INST1 - the command runs on all pins ...
    Posted to Digital Implementation (Forum) by mikhail on Tue, Nov 22 2011
  • Re: Danglling wires after LVS
    What do you see on these markers? Is it opens? It can be caused by missing wires between rings/stripes and std cells rails. [quote user="ssuhas"]What is the reason for the error and how do we debug it?[/quote]  Please attach a screenshot for one of violations. It will help to debug it.  
    Posted to Digital Implementation (Forum) by mikhail on Fri, Nov 19 2010
  • Re: Stream Out from Virtuoso
     H, You need to check options form on Stream Out form. If you should see "Translate Entire Hier" on General tab and on Libraries tab you need to get free list of reference libraries because cells from ref libs are just referenced in resulting gds. Hope this helps. Mikhail.
    Posted to Digital Implementation (Forum) by mikhail on Thu, Apr 29 2010
  • Re: Short between IO filler blockage and IO pad pin
    To avoid shorts you have at least 2 ways: 1. If blockage represents actual wire in the filler (not pad ring) then shorts are valid and you need to resize pad pin in IO cell to meet spacing (maybe you need to consider width-depended spacing rules). 2. If blockage comes from pad ring wires in the fille, then you need to define related pins in ...
    Posted to Digital Implementation (Forum) by mikhail on Wed, Apr 28 2010
  • Re: how to automatically add connections to global nets in Encounter
    In case you have a multysupply/multivoltage design you need to take care about CPF. For a rest designs you typically need just few global net connections (for core instances and pads). So, I suppose that using wildcard solution shown by Kari is suitable for most of designs.
    Posted to Digital Implementation (Forum) by mikhail on Tue, Apr 20 2010
  • Re: custom placement
    Hi, Also what do you need to place? Standard cell or block/guide/fence?
    Posted to Digital Implementation (Forum) by mikhail on Tue, Apr 20 2010
  • Re: Generation of tcf
    You have to run testbench with enabled PLI from RTL compiler installation.Also testbench should be modified in way to start toggle counting and save resulting tcf. After that you can load tcf file. Another way is to specify a switching activity by rc commands. Please let me know if you need a details.
    Posted to Digital Implementation (Forum) by mikhail on Mon, Apr 19 2010
  • Re: Power routing issues
    Hello, Am I right that DRCs are between power rings/stripes/pins and signal wires? Mikhail 
    Posted to Digital Implementation (Forum) by mikhail on Mon, Apr 19 2010
  • Re: DRC violation after trial routing
    Hi, Trial routing is dirty routing that typically used for estimation. So, DRC violations are expected. But if they still exist after Nanorouting (I mean the same violations) you need to check that dirty routing is deleted by NanoRoute before performing actual global/detail phase. Use editDelete -type Signal to delete all signal wires before ...
    Posted to Digital Implementation (Forum) by mikhail on Mon, Apr 19 2010
Page 1 of 1 (9 items)