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 Community Search 

Page 1 of 1 (7 items)
  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
     Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog, I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time to tapeout.  Anyone remember ...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
  • EDA Follow-The-Leader ... Signoff In The Design Flow
    As a member of the EDA community, I find it interesting and somewhat frustrating to see how much we copy each other at times. Ever notice how one company might make a position on something, and once their message resonates, then a lot of other companies come out of the woodwork with me-too messaging and positioning? I saw this happen on ...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, Aug 9 2010
  • Mixed Signal: Why The Sudden Attention?
    With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors will use “mixed signal” somewhere in their company’s messaging. Last year it seemed that nearly everyone wanted to jump on the mixed signal “bandwagon” … so what caused this sudden jump in interest in mixed signal? We all know that mixed signal design is not ...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, May 24 2010
  • Hands Up, Anyone Believe That Toyota's Problems Are All Physical?
    In the past number of weeks/months we have all seen how Toyota has struggled to manage perception around their "sudden acceleration" problems. The first fix that was proposed was a replacement of the floor mats, under the argument that the mats had been forcing the gas pedal down. Quickly following this first "solution", ...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, Apr 26 2010
  • IR Drop Analysis: It's Not Really Necessary, Is It?
    I was recently asked by an engineering manager if running IR drop analysis was really necessary. The argument to support his question was that his engineering team always over-designs the power rails, and so the risk of getting high IR drop was so small that analysis was not required. The easiest way to answer his question was to relate ...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, Apr 5 2010
  • Design Signoff Begins In Implementation
    As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes executing parasitic extraction that feeds ...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010
  • VoltageStorm Is Alive and Kicking!
    If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is “a lot”. If you have read my ...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, Apr 27 2009
Page 1 of 1 (7 items)