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 Community Search 

Page 1 of 4 (40 items) 1 | 2 | 3 | 4 | Next >
  • BSIM3 vs BSIM4
    Hi All, I have I think  trivial question I just want to confirm. I am using virtuoso 5.1 with spectre sub-version 11.1 for an old 180nm PDK having an old spice model (header as below) : MODEL: BSIM3 (V2.24) DATE: Sep 12, 2004 SPECTRE VERSION: V5.0.32.500.2 As I get some strange simulation result in a particular case, I wanted to try ...
    Posted to Custom IC Design (Forum) by isazulkc on Mon, Mar 24 2014
  • Re: LVS issue: short between global net VSS! and gnd
    Hi Andrew, The cds_thru generated a 100 mOhms resistance that don't directly pass LVS. Finally, I just had to edit/add  netset properties to the cell to link the global net in its schematic to the real power and ground in the top schematic. Thanks, Regards, KC 
    Posted to Custom IC Design (Forum) by isazulkc on Thu, Mar 6 2014
  • LVS issue: short between global net VSS! and gnd
    Hi, I' m using PVS 12.1 in IC6 to do LVS and  I have that issue: One cell used in the schematic has a global net VSS! and VDD!. In the top schematic and layout,the power is vdd and ground is vss. So the LVS fails and complains about VSS! shorted to vss and VDD! shorted with vdd. Is there a way to make the LVS understand there are the ...
    Posted to Custom IC Design (Forum) by isazulkc on Tue, Mar 4 2014
  • Re: Transient simulation display time issue !
    Hi, The issue has been resolved by closing Cadence and restarting the computer. I still don't understand why that limitation happened but it is OK now. K.C.
    Posted to Custom IC Design (Forum) by isazulkc on Wed, Dec 11 2013
  • Transient simulation display time issue !
    Hi, I am using IC5.1.4 with spectre simulator for transient simulations, and the issue I have is that the transient signals display seems to be limited at ~18 ms. Indeed, all transient signals stop at ~ 18ms even if the stop time is longer. For example when I do a 30 ms transient simulation, I can see in the log file that the simulation is 100% ...
    Posted to Custom IC Design (Forum) by isazulkc on Tue, Dec 10 2013
  • Re: DC sweep with ams simulator ?
    Hi Andrew, Yes in this present case I can do the characterization I want with parametric analysis ( that is check an analog output controlled by a config register for different DC input current). It is only longer, that's why I was tring DC sweep.  Regards,  Kc.
    Posted to Custom IC Design (Forum) by isazulkc on Thu, Jul 4 2013
  • DC sweep with ams simulator ?
    Hi,  I'm using IC5.1.4 and I would like to do a DC sweep simulation with ams on my mixed-signal design. However the DC sweep is not possible from the ams simulator GUI. So, how can I run a DC sweep simulation with AMS ? Thanks, Best Regards. Kc.
    Posted to Custom IC Design (Forum) by isazulkc on Thu, Jul 4 2013
  • Re: streamOutKeys error with IC6.1.5 ?
    Hi Andrew, Thanks, it works now :). I just had to change "#" by ";" for the comments cause "#" was considered as an illegal character when not at the beginning of a line. Best Regards, Kc.
    Posted to Custom IC Design (Forum) by isazulkc on Thu, May 30 2013
  • streamOutKeys error with IC6.1.5 ?
    Hi,  I am trying Cadence IC6.1.5 and it seems to have some problem with the streamOutKeys syntax. Is there a new streamOutKeys syntax for IC6.1.5? I have a template.layout file (see below) to directly fill the calibre layout export setup. This template.layout file is the one I used for Cadence IC5.1.4  and it works fine. ...
    Posted to Custom IC Design (Forum) by isazulkc on Thu, May 23 2013
  • Re: zero diagonal found in Jacobian
    Hi Quek, I'm using now Spectre 11.1.0.550.isr16.  With this version of Spectre there is no more jacobian warnings with Spectre simulator (at least in the ones I have done so far), but it still appear during some AMS simulations.< Best regards, KC
    Posted to Custom IC Design (Forum) by isazulkc on Mon, Dec 3 2012
Page 1 of 4 (40 items) 1 | 2 | 3 | 4 | Next >