Home > Community > Search

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Community Search

Find results with all the words
Matching all the tags
Written by
Scope

Page 1 of 1 (8 items)

RE: Package monitor_pkg could not be bound.
You can import the package after it’s description: package pkg_test; import pkg_xxx::*; .. … …. endpackage // pkg_test import pkg_test::*; Dima

Posted to Functional Verification (Forum) by Brodov Dmitriy on Tue, Oct 30 2012
RE: Internal error during elabration phase
Any PLI you load ? any models ? Best regards, Brodov Dmitriy

Posted to Functional Verification (Forum) by Brodov Dmitriy on Tue, Sep 4 2012
RE: Internal error during elabration phase
Auto-repeat

Posted to Functional Verification (Forum) by Brodov Dmitriy on Tue, Sep 4 2012
Re: Internal error during elabration phase
Kaleem, Please look above in the log file - usually the reason may be found there. Something like missing/ uncompelled system task/library or PLI. Dima

Posted to Functional Verification (Forum) by Brodov Dmitriy on Tue, Sep 4 2012
Re: How will I do a HAL Hdl analysis on vhdl design?
Hello, You can use cadence quick help for more explanation: nchelp ncvhdl_p LIBNOM ncvhdl_p/LIBNOM = The logical library name indicated is not mapped to a design library. Section [11.2] of LRM [87 & 93]. A user option file entry of the form: ...

Posted to Hardware/Software Co-Development, Verification and Integration (Forum) by Brodov Dmitriy on Mon, Jun 25 2012
Re: Elaboration error in SVA binding file
You can see a short help for this error by command: <nchelp ncelab NOBNDT> ncelab/NOBNDT = The above error has occurred because the target module or instance specified in the bind statement is not found. Check the target given with the bind ...

Posted to Functional Verification (Forum) by Brodov Dmitriy on Thu, Jun 7 2012
Re: Gate Level simulation for Big(Huge) chip
Steve, Thank you very much for your answer. Palladium sound interesting, but expensive ;-) Turning off all the timing checks is not such a good options since "timing checks" is one of issues that are not fully covered by STA. Right now i am checking the splitting of Netlist/SDF files and how the verification env. will handle ...

Posted to Functional Verification (Forum) by Brodov Dmitriy on Wed, Mar 18 2009
Gate Level simulation for Big(Huge) chip
Hello! I have the target of running the Gate Level (GTL) simulation for large chip. The GTL simulation is very, very slow and impossible to debug in such conditions. Is any one familiar with the solution to fast up the simulation: It could be tools or some sort of hierarchy design/SDF, Netlist splitting and etc? Thank you for the help ;-)BR, ...

Posted to Functional Verification (Forum) by Brodov Dmitriy on Tue, Mar 17 2009

Page 1 of 1 (8 items)

Email

Share

Subscribe

Contact Us

Community Search