Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (1 items)
  • DIVA LVS Error
    Forum users, I've created a schematic and layout of a simple cell using IC6.1.0 and trying to perform DIVA LVS by invoking it from the Virtuoso Layout L window by selecting Verify->LVS...  I am getting an error that I think signifies that the layout is failing to netlist.  Please see attached figure showing output error ...
    Posted to Custom IC Design (Forum) by saullacour on Mon, Apr 23 2012
Page 1 of 1 (1 items)