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Page 1 of 145 (1450 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: Change NetName
    I don't think that you have appreciated the way that the net name works. The name for a DboWire is assigned by Capture, N<some sequence number> is assigned and that is the Name of the Wire in the Capture DSN data, this can be overridden with a Net Alias, for example; more strictly a "higher order object": Net Alias, ...
    Posted to PCB Design (Forum) by oldmouldy on Fri, Sep 26 2014
  • Re: Change NetName
    You won't be able to change the name of a net in Capture, that's not even possible through the UI. Net Names get overridden with Net Aliases, you should be able change a Net Alias using an AliasIter on DboWire to scan the Aliases and the DboAlias object.
    Posted to PCB Design (Forum) by oldmouldy on Fri, Sep 26 2014
  • Re: Which separator use for list in drawing property "Jumper_list"?
    Apologies, I just found the documentation! A ":" would be a more common delimiter for list options. I will get this reported and see if the document can be updated.
    Posted to PCB Design (Forum) by oldmouldy on Fri, Sep 26 2014
  • Re: AMS & Pspice guidance
    Any simulation is going to depend upon being able to get models for the various elements of the circuit, just to get "any" result, and then how accurate those models are to determine "how close to reality" the modelled system is. At the basic level in PSpice, "wires" are assumed to be "perfect", component ...
    Posted to PCB Design (Forum) by oldmouldy on Thu, Sep 25 2014
  • Re: AMS & Pspice guidance
    Look in the PSpice Users Guide, pspug.pdf in the doc\pspug directory of the installation as a start. It sounds like you might have some confusion between PSpice, simulates components in a schematic and Signal Integrity, simulates routed connections in a PCB. (In simple terms), So the usual PSpice flow would be: start Capture (CIS) with ...
    Posted to PCB Design (Forum) by oldmouldy on Thu, Sep 25 2014
  • Re: How to display voltage through a resistor?
    Voltage drop is not an available Bias Marker so it is not possible to display this in the schematic canvas.
    Posted to PCB Design (Forum) by oldmouldy on Wed, Sep 24 2014
  • Re: Component placement is been not get updated
    It's quite hard to tell from the screen shot but, usually, issues when placing, or moving, components, check that the origin for the drawing that contains the symbol is within the symbol, typically Pin 1 for through hole components and Body Centre for surface mounted parts. Also check the "Point" for Move in the Options tab is set to ...
    Posted to PCB Design (Forum) by oldmouldy on Wed, Sep 24 2014
  • Re: Which separator use for list in drawing property "Jumper_list"?
    See the propref.pdf, in the doc\propref directory of the installation, semi-colon is the required delimiter for the jumper list.
    Posted to PCB Design (Forum) by oldmouldy on Wed, Sep 24 2014
  • Re: fanout problem in allegro pcb editor
    Try setting the Thermal Connections to "Full Contact" before autorouting, Shapes>Global Dynamic Params, Thermal Relief Connects tab, set the Thru Pins to Full Contact. Also don't add shapes the layers that the autorouter is going to use, before autorouting. If you need shapes on the layers that the autorouter is going to use, ...
    Posted to PCB Design (Forum) by oldmouldy on Mon, Sep 22 2014
  • Re: [ALG0065] Illegal character in \ in design ??
    Check the paths of any parts in the design cache, you will need to eliminate the braces "()"
    Posted to PCB Design (Forum) by oldmouldy on Thu, Sep 18 2014
Page 1 of 145 (1450 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »