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Page 1 of 1 (5 items)
  • Re: ELC not using spectre
    It's already there.
    Posted to Digital Implementation (Forum) by Khenglish on Fri, Jul 25 2014
  • Re: ELC cannot run db_spice
    I noticed that your setup file is a direct copy from the Erik Brunvand book.  Since you are using a TSMC process, I'm assuming it is relatively modern, but you are using voltage parameters that correspond to the 600nm MOSIS process that Brunvand was using.  You are calling for threshold voltages that are completely impossible, and ...
    Posted to Digital Implementation (Forum) by Khenglish on Thu, Jul 24 2014
  • Re: ELC not using spectre
    I fixed the one error.  It was because when fixing my file format for ELC I accidentally messed up the inputs to that diode.  It is not giving me an error that it cannot find the ASSERT subckt.  I'm pretty sure this is a spice vs spectre error since ASSERT is not a circuit, but a spectre command to verify proper output. Again ...
    Posted to Digital Implementation (Forum) by Khenglish on Thu, Jul 24 2014
  • ELC not using spectre
    ELC seems to always read in files as spice format even though I have "simulator lang = spectre" without the quotes at the top of every .scs file.  In addition I have: set_var EC_SIM_NAME "spectre" set_var EC_SIM_TYPE "spectre" in my script every time before I do any database operation. These are the types of ...
    Posted to Digital Implementation (Forum) by Khenglish on Wed, Jul 23 2014
  • Implement TSGEN in IBM 9HP process
    I made several behavioral designs in Verilog that use tri-state buffers.  Structural Verilog from Synopsys uses the TSGEN function to implement tri-state buffers, but the tech library does not seem to have TSGEN implemented, and attempting to place & route results in the tri-state outputs being unconnected.  How do I get on the path to ...
    Posted to Digital Implementation (Forum) by Khenglish on Tue, Jul 8 2014
Page 1 of 1 (5 items)