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Page 1 of 1 (5 items)
  • Re: How to define a binary matrix parameter in Verilog A
    Thank you Andrew, here is the heading of my spectre.out . Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 10.1.1.441.isr25 32bit 25 Jul 2012 Copyright (C) 1989-2012 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc.  Protected by ...
    Posted to Custom IC Design (Forum) by microstudent on Wed, Jun 4 2014
  • How to set bindkeys of Virtuoso alignment window
    I have a question about how to set bindkeys of Virtuoso Layout alignment window, I can pop up this window by setting lxHiAlign(), but when the window appears, I don't know how to set bindkeys for example "Alignment Direction", I would prefer a bindkey to choose this two options, and the button of Set New Reference. Thank you in ...
    Posted to Custom IC Design (Forum) by microstudent on Tue, Jun 3 2014
  • Re: How to define a binary matrix parameter in Verilog A
    Hi Andrew, Thank you again for your help! The reason I added the line     val[i]=data_pattern[i]*0; is to get my simulation runing, what I intend to do is making     val[i]=data_pattern[i]*V(VDD); however, the data_pattern[0] in my simulation returns to be 01111111111111111111111111111111, this gives ...
    Posted to Custom IC Design (Forum) by microstudent on Tue, Jun 3 2014
  • Re: How to define a binary matrix parameter in Verilog A
    Hi Andrew,                 Thank you very much for your reply! Here is the code: `include "constants.vams“ `include "disciplines.vams" module data_pattern_gen(DATA,VDD,VSS); output [15:0] DATA; electrical [15:0] DATA; inout VSS; electrical VSS; inout ...
    Posted to Custom IC Design (Forum) by microstudent on Mon, Jun 2 2014
  • How to define a binary matrix parameter in Verilog A
    Hi guys, I have a question about how to define a binary matrix parameter in Verilog A. For example, I can define parameter as data_pattern[15:0]={0,0,0,.....,0}. To my knowledge, each bit of data_pattern[15:0] are 32bit integer, for me I only want data_pattern to be a 16-bit binary. After run the code (attach on this post), the ...
    Posted to Custom IC Design (Forum) by microstudent on Fri, May 30 2014
Page 1 of 1 (5 items)