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 Community Search 

Page 1 of 1 (7 items)
  • conformal LEC
    Can anyone tell why this is happening "Inserted DC(s) due to DFF clock/data interaction" and will it cause any false non -equivalency?     
    Posted to Logic Design (Forum) by Indira S on Sun, Apr 13 2014
  • conformal
    I am verifying a rtl vs DC netlist. The verification passes only if I set one of the Asynchronous reset to 0. otherwise in revised design the reset value is not attended whereas in golden design reset is 1 
    Posted to Logic Design (Forum) by Indira S on Tue, Feb 11 2014
  • conformal lec
    Hi During comparison I get some non-equivalent points. Some non equivalencies are due to " DC due to clock/data interaction and DC due to asynchronous interaction". Due to this in Golden, the input to a select input of mux is 1 and that to the revised is X. What is the solution ?. Kindly reply. 
    Posted to Logic Design (Forum) by Indira S on Mon, Feb 10 2014
  • conformal
    Does conformal lec support VSDC files which contain information about synthesis optimisations ?
    Posted to Logic Design (Forum) by Indira S on Thu, Jan 30 2014
  • conformal_lec 12.0
    HI I have an RTL and netlist from DC compiler. My library files are .lib files and I read them as liberty libary files. Do I have to designate the library both to RTL and Netlist. I f I do so I get some error like cant find a pin x. So I read the library only for the revised netlist. Also in non - equivalent points, the bbox is non equivalent ...
    Posted to Logic Design (Forum) by Indira S on Wed, Jan 29 2014
  • conformal -Lec
    I am verifying a RTL vs NEtlist created by synopsys DC compiler. Some modules are black boxes by the tool. I think they are some memory modules. What is the way to preserve the interface information of the black box ie only the boundary info. 
    Posted to Logic Design (Forum) by Indira S on Tue, Jan 28 2014
  • Conformal- LEC
    Hi When I run Hirarchial compare using conformal, write hier_compare dofile dofile.do is not created. It is throwing the error like "could not find the starting comment hierarchial do file generated by conformal when I run run hier_compare. When I setup the design I got the message like $ modules are output for Hierarchial do file yet the do ...
    Posted to Logic Design (Forum) by Indira S on Thu, Jan 16 2014
Page 1 of 1 (7 items)