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 Community Search 

Page 1 of 2 (13 items) 1 | 2 | Next >
  • Re: AMS simulation questions
    I made some progress on this but I could still use some help. I gave up on using a VerilogD testbench (due to limited support for real numbers) and focused instead on SystemVerilog and Verilog-AMS. The out of module refereces (OOMR) work with the setup listed below. It seems that everything is fine and E2R/R2E conversion blocks are inserted if I ...
    Posted to Mixed-Signal Design (Forum) by Octavian on Wed, Jul 2 2014
  • AMS simulation questions
    I have a top level verilog testbench instantiating an analog spectre module (subckt). I can run a transient simulation with the Incissive irun flow but I could not figure out how to do the following: - sample an internal voltage/current in the analog module and use that in the verilog code to make a decision: if ( V(I0.I0.I0.analog_node) > 1 ...
    Posted to Mixed-Signal Design (Forum) by Octavian on Mon, Jun 30 2014
  • Re: Virtuoso Editor Tools Menu
    Thanks for the reply.  That's good information. I access the license server using a slow connection so this could definitely be the issue.   --Tavi 
    Posted to Custom IC Design (Forum) by Octavian on Mon, Apr 28 2014
  • Virtuoso Editor Tools Menu
      When I first click on the "Tools" menu in the Virtuoso Schematic/Layout editor the entire Cadence GUI freezes for up to 30 seconds. This does not happen on any subsequent times I click on the Tools menu, even from different windows. My guess is that it tries to find what tools are available and build that menu on the fly. If ...
    Posted to Custom IC Design (Forum) by Octavian on Mon, Apr 28 2014
  • Re: IC5141 environment setup
    Thanks for the reply.   I also found out that the ASSURA version must match the version of the IC installation. So for IC5141 that would be ASSURA41-5141-.... The INCISIVE release notes (*.txt) file have the number for the compatible MMSIM version.
    Posted to Custom IC Design (Forum) by Octavian on Mon, Apr 7 2014
  • IC5141 environment setup
    I'm setting up a custom design environment based on the latest hotfix release of IC5141 (version 5.10.41.500.6.151 ) and I'm a little confused on which additional packages/versions I need to install to get the following features: - lvs/drc (ASSURA?) - postlayout parasitics extraction (EXT?) - analog design environment with spectre and ...
    Posted to Custom IC Design (Forum) by Octavian on Wed, Mar 26 2014
  • Re: Generate netlist with subckt statement for top level
     It works!  Thank you.
    Posted to Custom IC Design (Forum) by Octavian on Wed, Mar 26 2014
  • Re: Generate netlist with subckt statement for top level
    Thanks for the prompt reply. Is there a similar solution for IC514?   Thanks, --Tavi
    Posted to Custom IC Design (Forum) by Octavian on Wed, Mar 26 2014
  • Generate netlist with subckt statement for top level
    I'm generating a netlist from CIW using: simulator('spectre) design("libName" "cellName" "viewName") createNetlist() This works fine but I would like to enclose the top level cell in .subckt/ends statements, similar to other cells in the hierarchy. Is that possible using the skill/ocean ...
    Posted to Custom IC Design (Forum) by Octavian on Tue, Mar 25 2014
  • Re: Disable "Save Display Information" form
    Thanks for the quick reply  But this will cancel the form even when other modifications were made to the display information. I'm thinking about creating a temporary drf file with my modifications and loading that with drLoadDrf. Will that work?
    Posted to Custom IC Design (Forum) by Octavian on Fri, Mar 14 2014
Page 1 of 2 (13 items) 1 | 2 | Next >