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Page 1 of 2 (12 items) 1 | 2 | Next >
  • Re: Analog-Env Sim Error
    Actually your method works. Sorry, it was an error on my part (edited the wrong library).
    Posted to Custom IC Design (Forum) by tempVar on Thu, Dec 5 2013
  • Re: Analog-Env Sim Error
    Hey. Thank you Andrew for your help and input. So I tried simply renaming them (and checking the "Update instances" button) but that did not work : ( I did however manage to rename all of them using another technique:  I clicked on one instance of a component (say, my previously named "2to4decoder")Hit ...
    Posted to Custom IC Design (Forum) by tempVar on Thu, Dec 5 2013
  • Re: Analog-Env Sim Error
    Hello again. Thank you for your reply, your solution worked!  I do however have another problem now, When I update my symbols' names, the instances used in the main schematic do not update : ( Do I need to manually update them (or redo the schematic)? Or is there away to automatically update all instance cell names from their symbol cell ...
    Posted to Custom IC Design (Forum) by tempVar on Thu, Dec 5 2013
  • Analog-Env Sim Error
    Hi. Here is my situation: I worked on a schematic for a 2to4 decoder, saved and checked with no problem. Opened Analog Environment and hit run and simulate. Everything works with no errors. I made a symbol for this 2to4 decoder.  I then opened a new schematic, inserted a decoder. Opened Analog Environment, tried to run simulation... icfb ...
    Posted to Custom IC Design (Forum) by tempVar on Wed, Dec 4 2013
  • Re: LVS LAYOUT debug?!
    Thank you, I have fixed the error you found, along with many others and have got it to work. I am now having a problem with a simple nor gate layout, would it be possible to help me with that?   
    Posted to Custom IC Design (Forum) by tempVar on Tue, Nov 12 2013
  • LVS LAYOUT debug?!
    Hello all. First, I need to let you know that this is my first layout that contains more than 2 transistors, so excuse my noobish methods. I am trying to make a 2-input xor gate. I have run DRC with no errors. I run LVS and get a couple of errors, I cannot seem to fix them, so any help will be much appreciated. I will provide screenshots for the ...
    Posted to Custom IC Design (Forum) by tempVar on Mon, Nov 11 2013
  • Re: Hierarchy and layouts?
     Thank you very much for your help. That is what I will be doing. 
    Posted to Custom IC Design (Forum) by tempVar on Sun, Nov 10 2013
  • Hierarchy and layouts?
    Hey all. I am about to start working on an adder. I have to make a schematic and layout. My question is, is it possible to have each symbol have its own layout, and then use that smybol in a layout? So for example have a layout for a 1bit full adder and then merge 4 1bit-full adders into one big layout? I know you can do this with schematics, but ...
    Posted to Custom IC Design (Forum) by tempVar on Thu, Nov 7 2013
  • Re: CMOS INVERTER LAYOUT DEBUG!?
    Fixed! It is kind of obvious where the problem is! If you can tell the nmos seems to be working properly (as seen in the wave forms). It is the pmos part that seems to be messed up, it is also apperent that the pmos is simply not doing anything or in other words; not functioning... Hmmmm, what may cause such an issue? THINK ABOUT IT!!!  Done ...
    Posted to Functional Verification (Forum) by tempVar on Sat, Oct 19 2013
  • CMOS INVERTER LAYOUT DEBUG!?
     Hello all. So I am in the process of simulating my layout extraction. I ran DRC which was successful.I ran LVS which returned a negative output (my schematic netlist and extracted netlist DO NOT MATCH);however, I continued with the simulation hoping to see if I can gain some info from the plots...   Here is my layout and the plot ...
    Posted to Functional Verification (Forum) by tempVar on Sat, Oct 19 2013
Page 1 of 2 (12 items) 1 | 2 | Next >