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Page 1 of 1 (4 items)
  • Re: Custom deep trench capacitor
     So could you point me on how to change the calculated capacitance value generated by the area of the capacitor when laying it out? I am really in over my head here..........
    Posted to Custom IC Design (Forum) by madhanmo on 06-20-2014
  • Custom deep trench capacitor
    Hi, I am starting out with a project on DRAM memory cells and am using the cadence 45nm tech node. But at this technology, the capacitance from the mimcap and moscaps need a large area. So I was wondering whether there is any way I would be able to add a custom deep trench capacitor to the technology. Please guide me on what I can do at this ...
    Posted to Custom IC Design (Forum) by madhanmo on 06-19-2014
  • Grid spacing for 45nm GPDK process
    Hi, Could anyone please point me to the optimal minor and major spacings and the snap spacings for the 45 nm gpdk process?am having a hard time finding those values
    Posted to Custom IC Design (Forum) by madhanmo on 06-11-2014
  • Error when trying to add stimuli in virtuoso
    I create a basic inverter and launched ADE L and tried to add the stimuli for the circuit and it comes up with the following error *Error* Could not find source, vdc, in analogLib. I am using NCSU cdk 1.6 beta(latest version as of now) some one please guide me on how to solve the above error 
    Posted to Custom IC Design (Forum) by madhanmo on 10-10-2013
Page 1 of 1 (4 items)