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 Community Search 

Page 1 of 1 (9 items)
  • Error on creating wire in Virtuoso
     Hi, When i'm trying to create a wire in Schematic editor of cadence Virtuoso i'm getting the following error and wire is not getting created. I'm able to copy/move/extent the already existing wires though.. "Loading layers.cxt * Field is "color" * *Error* hiCreateCyclicField: value must be ...
    Posted to Custom IC Design (Forum) by Shameel on Wed, Jan 29 2014
  • Simulating with 48 pin QFN package
     Hi,  I want to simulate my design (done with IO planning in encounter) with 48 pin QFN Package. Kindly help me on which tool,and what all inputs I need for that?    Thanks Shameel
    Posted to IC Packaging and SiP Design (Forum) by Shameel on Sun, Oct 27 2013
  • Query on necessity of Filler Cells in a small custom design - Virtuoso
     Hi , I am doing a custom design in virtuoso (Digital) in which I am connecting all Nwell & Pwell manually to VDD and GND . Then do I really need filler cells before a tapeout? Thanks
    Posted to Custom IC Design (Forum) by Shameel on Sun, Oct 27 2013
  • Re: Writing out .lib & lef from virtuoso
    Hi Alex, I have made the option " CIW -> Tools -> Set cellType>   *   " Still encounter does n't recognize it as MACRO If I change CLASS to PAD instead of CORE or BLOCK ,encounter is recognizing it as IO pad with pins and exactly how I need it; except that it is IO . But its not supporting ...
    Posted to Custom IC Design (Forum) by Shameel on Tue, Oct 8 2013
  • Re: Writing out .lib & lef from virtuoso
    Hello Andrew, Thanks for the help.. The issue with lef is that  once I export  lef from virtuoso and read this to encounter,its not recognised by encounter as a macro. Can we use the lef generated by  File->Export->LEF in virtuoso directly to encounter ? Or anything else need to be done for generating abstract  views ...
    Posted to Custom IC Design (Forum) by Shameel on Mon, Oct 7 2013
  • Writing out .lib & lef from virtuoso
     Hi All How can I write out .lib file of a digital module designed in virtuoso ? Also If I want to import this module as a digital block to encounter, how can I make it as a macro/cell ? How to take care of this while writing out lef from virtuoso ?   Thanks Shameel
    Posted to Custom IC Design (Forum) by Shameel on Sun, Oct 6 2013
  • IO placement
       Hi All,  I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it. ===================================================== --> <folderPath>/BackEnd/ * LEF P & R model         ...
    Posted to Custom IC Design (Forum) by Shameel on Wed, Sep 25 2013
  • Virtuoso 6.1.5 to encounter
     Hi All,  I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it. ===================================================== --> <folderPath>/BackEnd/ * LEF P & R model             (in ...
    Posted to Digital Implementation (Forum) by Shameel on Wed, Sep 25 2013
  • Virtuoso 6.1.5 to encounter
     Hi All,  I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it. ===================================================== --> <folderPath>/BackEnd/ * LEF P & R model             (in ...
    Posted to Digital Implementation (Forum) by Shameel on Wed, Sep 25 2013
Page 1 of 1 (9 items)