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Page 1 of 1 (2 items)
  • Veriloga Montecarlo input from spectre
    Dear,   I am trying to add montecarlo mismatch into a verilogA model (delay variation) using IC6.1.5. I read on several post to use a custom scs model file that includes the verilog file and has a STAT section to define parameter variations. (like this http://www.cadence.com/Community/forums/t/27475.aspx). I dont know how to go further. Is ...
    Posted to Custom IC Design (Forum) by jeffreyprin on Thu, Dec 12 2013
  • Layout pin problem: net name distributes via transistor
    Hi, I am facing a problem in the layout. I designed a DRC free inverter using the gpdk90nm package from pdk.cadence.  The final step of placing pins in the circuit invokes net connection errors. When the Out pin of the inverter is placed on the layout, the metal of vdd (not yet assigned) and gnd (not yet assigned) also gets the net name ...
    Posted to Custom IC Design (Forum) by jeffreyprin on Fri, Sep 20 2013
Page 1 of 1 (2 items)