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 Community Search 

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  • Syntax V93 VHDL
     Hi there,   I am building an ip, i tested it on Xilinx FPGA is seems works    now i m testing it on virtuoso cadence and give me this 2 errors, someone can help please  1) ------------------------------------- E,MLTDRV (./test.vhdl,17|0): Signal/register 'M_ADDR' has multiple drivers. ------ The specified ...
    Posted to Digital Implementation (Forum) by tonio on Mon, Jan 13 2014
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