Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (1 items)
  • Syntax V93 VHDL
     Hi there,   I am building an ip, i tested it on Xilinx FPGA is seems works    now i m testing it on virtuoso cadence and give me this 2 errors, someone can help please  1) ------------------------------------- E,MLTDRV (./test.vhdl,17|0): Signal/register 'M_ADDR' has multiple drivers. ------ The specified ...
    Posted to Digital Implementation (Forum) by tonio on Mon, Jan 13 2014
Page 1 of 1 (1 items)