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 Community Search 

Page 1 of 1 (7 items)
  • relxpert vth degradation
    Hi All, I tried the example provided by Cadence with Relxpert and the output .bo0 file showed the vth degradation. The manual did not mention the units. Is it milli volts? Also, I tried the tool with a simple nand gate example using a static vector A=1, B=1. So both the pmos are in OFF mode. The Relxpert still shows a non-zero Vth degradation. ...
    Posted to Digital Implementation (Forum) by Shiny on Fri, Aug 29 2014
  • Re: encounter streamout by preserving the partition
    Hi Brian, I tried converting my transistor level hspice netlist of sensor into lef format, instantiated in verilog  and did place-and-route in encounter. But in place phase, the standard cells are populated in the entire circuit except  in the sensors since the are not described as netlist with standard cells to start with. In the final ...
    Posted to Digital Implementation (Forum) by Shiny on Sun, Aug 4 2013
  • encounter streamout by preserving the partition
    Hello All,I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted spice netlist using divaEXT.rul. My experimentation is supposed to be on the spice netlist.The problem is I need to insert sensors in the filter ...
    Posted to Custom IC Design (Forum) by Shiny on Thu, Aug 1 2013
  • Re: encounter streamout by preserving the partition
    Thanks Brian! I will look into that.
    Posted to Digital Implementation (Forum) by Shiny on Thu, Aug 1 2013
  • Re: encounter streamout by preserving the partition
    Hi Brian, Thanks for responding! I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted spice netlist using divaEXT.rul. My experimentation is supposed to be on the spice netlist. The problem is I need to insert ...
    Posted to Digital Implementation (Forum) by Shiny on Thu, Aug 1 2013
  • encounter streamout by preserving the partition
    After floorplanning my design in Encounter, I specified partition to few of my blocks in the design. I did gds streamout and imported the .gds file to virtuoso. The netlist extracted from virtuoso do not show the partitions. How should I preserve the partioning all the way until the netlist phase? Please help me out!
    Posted to Digital Implementation (Forum) by Shiny on Wed, Jul 31 2013
  • where to insert an additional transistor level circuit in digital flow?
    Hello All, I am performing a complete digital implementation flow to a given circuit. I started with behavioral vhdl, used Cadence Buildgates with osu018 std cell library and obtained structural verilog format. Next, I used Cadence SOC Encounter for place-and-route, exported .gds output format and imported into virtuoso to obtain a final layout ...
    Posted to Custom IC Design (Forum) by Shiny on Sun, Jul 28 2013
Page 1 of 1 (7 items)