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  • Re: Asynchronous FIFO design
     FIFO is nothing but a set of registers.Normally used in highthroughput requirement systems.Data read /write when FIFO empty /full creates issues ,so we need to design additional control logic for the same.My suggestion is to understand syncronous FIFO first ,then undestand the problem of metastability and CDC reconvergence ,followed by grey ...
    Posted to Logic Design (Forum) by Paul Bibin on Sat, Jul 20 2013
  • Re: how to add synthesizable delay in design
    At RTL stage you can add delays either by registers /counter However during backend phase delays can be incorporated by adding buffers /delay elements in the design.
    Posted to Logic Design (Forum) by Paul Bibin on Sat, Jul 20 2013
Page 1 of 1 (2 items)